LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Saturday August 03 2024 23:02:32 UTC

GitHub Revision: c8985d6745

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 108668412464624965510474525856307009670790505545344576298908689226672042444441

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	8.540s	125.864us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.140s	18.615us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.210s	18.216us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.040s	55.183us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.370s	17.784us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.870s	29.009us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.210s	18.216us	20	20	100.00
		lc_ctrl_csr_aliasing	1.370s	17.784us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	11.250s	93.592us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	22.800s	677.275us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.020s	14.022us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.990s	150.484us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	38.970s	924.560us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	20.970s	4.773ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	38.970s	924.560us	50	50	100.00
		lc_ctrl_prog_failure	5.990s	150.484us	50	50	100.00
		lc_ctrl_errors	20.970s	4.773ms	50	50	100.00
		lc_ctrl_security_escalation	19.160s	560.721us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.638m	4.165ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	21.290s	2.823ms	20	20	100.00
		lc_ctrl_jtag_errors	1.432m	15.434ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	17.080s	1.380ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	25.220s	2.626ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	21.290s	2.823ms	20	20	100.00
		lc_ctrl_jtag_errors	1.432m	15.434ms	20	20	100.00
		lc_ctrl_jtag_access	29.010s	5.152ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	40.970s	11.395ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.230s	209.967us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.280s	120.204us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	27.450s	1.242ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	20.110s	3.362ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.250s	111.358us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	7.430s	279.321us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.710s	170.696us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	54.740s	2.345ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.140s	16.853us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	9.792m	140.231ms	48	50	96.00
V2	alert_test	lc_ctrl_alert_test	1.450s	96.338us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.290s	106.758us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.290s	106.758us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.140s	18.615us	5	5	100.00
		lc_ctrl_csr_rw	1.210s	18.216us	20	20	100.00
		lc_ctrl_csr_aliasing	1.370s	17.784us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.870s	72.848us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.140s	18.615us	5	5	100.00
		lc_ctrl_csr_rw	1.210s	18.216us	20	20	100.00
		lc_ctrl_csr_aliasing	1.370s	17.784us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.870s	72.848us	20	20	100.00
V2		TOTAL			698	700	99.71
V2S	tl_intg_err	lc_ctrl_sec_cm	40.030s	832.938us	5	5	100.00
		lc_ctrl_tl_intg_err	4.320s	111.882us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.320s	111.882us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	22.800s	677.275us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	38.970s	924.560us	50	50	100.00
		lc_ctrl_sec_cm	40.030s	832.938us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	38.970s	924.560us	50	50	100.00
		lc_ctrl_sec_cm	40.030s	832.938us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	38.970s	924.560us	50	50	100.00
		lc_ctrl_sec_cm	40.030s	832.938us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	38.970s	924.560us	50	50	100.00
		lc_ctrl_sec_cm	40.030s	832.938us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	38.970s	924.560us	50	50	100.00
		lc_ctrl_sec_cm	40.030s	832.938us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	38.970s	924.560us	50	50	100.00
		lc_ctrl_sec_cm	40.030s	832.938us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	38.970s	924.560us	50	50	100.00
		lc_ctrl_sec_cm	40.030s	832.938us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	38.970s	924.560us	50	50	100.00
		lc_ctrl_sec_cm	40.030s	832.938us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	19.160s	560.721us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.250s	93.592us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	25.220s	2.626ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	22.090s	2.151ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	22.090s	2.151ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	25.390s	1.877ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	16.510s	856.103us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	16.510s	856.103us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	43.251m	43.469ms	28	50	56.00
V3		TOTAL			28	50	56.00
		TOTAL			1006	1030	97.67

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.86	97.92	95.75	93.40	97.62	98.52	98.51	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:836) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 19 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 19 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.99277285579008856481275851684175951147288476406204992774553129087401364711973
      Line 21890, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 15228871560 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 15228871560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.lc_ctrl_stress_all_with_rand_reset.113030241523099698534450212328699853689313219808205999437922810949628406492153
      Line 26644, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 18160379670 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 18160379670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 17 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 2 failures:

  • Test lc_ctrl_stress_all has 2 failures.

    • 30.lc_ctrl_stress_all.38539227539011813503118649810547743208864764517260761685735309212995602528579
      Line 6526, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 39345479536 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 39345479536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 35.lc_ctrl_stress_all.107838272389506379161172567424418052279531027380229472034514935392755385287969
      Line 3108, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 35550936025 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 35550936025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:548) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 30.lc_ctrl_stress_all_with_rand_reset.89524890858286367331266532784442820921511014841627946508455112554354457682290
      Line 17766, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 19957751599 ps: (cip_base_vseq.sv:548) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 19957751599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 36.lc_ctrl_stress_all_with_rand_reset.4279275341449385361013673169535615094731084862853636652305941367132188895997
      Line 30472, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 50733099827 ps: (cip_base_vseq.sv:548) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 50733099827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 24.lc_ctrl_stress_all_with_rand_reset.12149801406912508021607256660753385596483107895426217252476680548556711441854
      Line 46460, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

Past Results

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