LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Sunday August 04 2024 23:02:21 UTC

GitHub Revision: `c8985d6745`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107130591329296133632864610148388701578652631018704528920799220771546870921898

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	6.750s	168.289us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.320s	64.474us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.090s	16.444us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.810s	27.204us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.390s	122.775us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.290s	106.206us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.090s	16.444us	20	20	100.00
		lc_ctrl_csr_aliasing	1.390s	122.775us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	9.550s	198.777us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	11.070s	575.169us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.940s	22.932us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.860s	511.718us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	40.140s	2.347ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	21.950s	606.058us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	40.140s	2.347ms	50	50	100.00
		lc_ctrl_prog_failure	4.860s	511.718us	50	50	100.00
		lc_ctrl_errors	21.950s	606.058us	50	50	100.00
		lc_ctrl_security_escalation	18.400s	3.057ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.392m	12.892ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	26.660s	2.088ms	20	20	100.00
		lc_ctrl_jtag_errors	1.363m	19.988ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	12.170s	474.618us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	35.700s	1.005ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	26.660s	2.088ms	20	20	100.00
		lc_ctrl_jtag_errors	1.363m	19.988ms	20	20	100.00
		lc_ctrl_jtag_access	23.120s	992.978us	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	41.320s	3.161ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	5.300s	255.690us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.920s	1.073ms	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	54.560s	5.456ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	18.100s	3.114ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.800s	66.805us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	5.700s	236.137us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.580s	171.694us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	1.023m	5.843ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.220s	74.476us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	14.051m	276.546ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.290s	49.484us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.780s	117.024us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.780s	117.024us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.320s	64.474us	5	5	100.00
		lc_ctrl_csr_rw	1.090s	16.444us	20	20	100.00
		lc_ctrl_csr_aliasing	1.390s	122.775us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.950s	45.907us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.320s	64.474us	5	5	100.00
		lc_ctrl_csr_rw	1.090s	16.444us	20	20	100.00
		lc_ctrl_csr_aliasing	1.390s	122.775us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.950s	45.907us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	35.360s	612.550us	5	5	100.00
		lc_ctrl_tl_intg_err	4.270s	243.480us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.270s	243.480us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	11.070s	575.169us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	40.140s	2.347ms	50	50	100.00
		lc_ctrl_sec_cm	35.360s	612.550us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	40.140s	2.347ms	50	50	100.00
		lc_ctrl_sec_cm	35.360s	612.550us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	40.140s	2.347ms	50	50	100.00
		lc_ctrl_sec_cm	35.360s	612.550us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	40.140s	2.347ms	50	50	100.00
		lc_ctrl_sec_cm	35.360s	612.550us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	40.140s	2.347ms	50	50	100.00
		lc_ctrl_sec_cm	35.360s	612.550us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	40.140s	2.347ms	50	50	100.00
		lc_ctrl_sec_cm	35.360s	612.550us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	40.140s	2.347ms	50	50	100.00
		lc_ctrl_sec_cm	35.360s	612.550us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	40.140s	2.347ms	50	50	100.00
		lc_ctrl_sec_cm	35.360s	612.550us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	18.400s	3.057ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	9.550s	198.777us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	35.700s	1.005ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	25.570s	2.449ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	25.570s	2.449ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	29.700s	6.504ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	22.230s	2.797ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	22.230s	2.797ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	2.391h	57.808ms	24	50	48.00
V3		TOTAL			24	50	48.00
		TOTAL			1004	1030	97.48

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.82	97.92	95.66	93.40	97.62	98.52	98.51	96.11

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:836) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 21 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 21 failures.
  - 2.lc_ctrl_stress_all_with_rand_reset.89138136738730978512375780532451548423621075894564164542660341297557146541825
    Line 34839, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 30712695800 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 30712695800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.lc_ctrl_stress_all_with_rand_reset.84245666417088905190442708617621392920045369210498516219351416344628053006705
    Line 19692, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 111475359099 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 111475359099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 19 more failures.
Error-[CNST-STOF] Constraint solver timeout failure has 3 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 3 failures.
  - 16.lc_ctrl_stress_all_with_rand_reset.49715760593114415315389178172477194835985930769207747855469396893507601749339
    Line 41316, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Error-[CNST-STOF] Constraint solver timeout failure
  ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
    Exceeded cpu time limit during solve.
    Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
    limit.  The default cpu limit is 1000 seconds per partition.
```
  - 28.lc_ctrl_stress_all_with_rand_reset.33336285540282338988460961070334850111968992781211163830985494991081089879144
    Line 36969, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Error-[CNST-STOF] Constraint solver timeout failure
  ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
    Exceeded cpu time limit during solve.
    Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
    limit.  The default cpu limit is 1000 seconds per partition.
```
  - ... and 1 more failures.
UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 6.lc_ctrl_stress_all_with_rand_reset.111369766782870782760368056953814857848740788225278965152560436152176496875271
    Line 1286, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 22874221107 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
  UVM_INFO @ 22874221107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 11.lc_ctrl_stress_all_with_rand_reset.51143838022304309498811304345004645326717396499316066273911593862554919909155
    Line 13736, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 16693792675 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 16693792675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Sunday August 04 2024 23:02:21 UTC

GitHub Revision: c8985d6745

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107130591329296133632864610148388701578652631018704528920799220771546870921898

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `c8985d6745`