LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Monday August 05 2024 23:02:13 UTC

GitHub Revision: e4c5daa580

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 57478527486894479494471273459769404654835266620222125964939301612221385668501

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	9.130s	272.420us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.060s	17.962us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.140s	28.598us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.810s	95.037us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.690s	418.610us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.870s	47.765us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.140s	28.598us	20	20	100.00
		lc_ctrl_csr_aliasing	1.690s	418.610us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.180s	146.329us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	23.180s	1.754ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.970s	18.528us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.930s	431.654us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	34.620s	2.035ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	25.760s	704.362us	49	50	98.00
V2	security_escalation	lc_ctrl_state_failure	34.620s	2.035ms	50	50	100.00
		lc_ctrl_prog_failure	4.930s	431.654us	50	50	100.00
		lc_ctrl_errors	25.760s	704.362us	49	50	98.00
		lc_ctrl_security_escalation	18.200s	775.385us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.230m	8.785ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	25.820s	2.074ms	20	20	100.00
		lc_ctrl_jtag_errors	1.590m	14.128ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	11.660s	768.578us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	37.550s	1.144ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	25.820s	2.074ms	20	20	100.00
		lc_ctrl_jtag_errors	1.590m	14.128ms	20	20	100.00
		lc_ctrl_jtag_access	25.550s	4.509ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	30.330s	25.348ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	5.790s	997.779us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.360s	189.308us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	48.610s	2.327ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	14.420s	1.173ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.480s	30.877us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	5.890s	223.543us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.080s	53.865us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	11.250s	1.595ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.280s	40.578us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	10.810m	68.388ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.420s	28.736us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.330s	156.326us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.330s	156.326us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.060s	17.962us	5	5	100.00
		lc_ctrl_csr_rw	1.140s	28.598us	20	20	100.00
		lc_ctrl_csr_aliasing	1.690s	418.610us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.840s	67.655us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.060s	17.962us	5	5	100.00
		lc_ctrl_csr_rw	1.140s	28.598us	20	20	100.00
		lc_ctrl_csr_aliasing	1.690s	418.610us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.840s	67.655us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	41.750s	1.227ms	5	5	100.00
		lc_ctrl_tl_intg_err	3.910s	1.935ms	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	3.910s	1.935ms	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	23.180s	1.754ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	34.620s	2.035ms	50	50	100.00
		lc_ctrl_sec_cm	41.750s	1.227ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	34.620s	2.035ms	50	50	100.00
		lc_ctrl_sec_cm	41.750s	1.227ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	34.620s	2.035ms	50	50	100.00
		lc_ctrl_sec_cm	41.750s	1.227ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	34.620s	2.035ms	50	50	100.00
		lc_ctrl_sec_cm	41.750s	1.227ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	34.620s	2.035ms	50	50	100.00
		lc_ctrl_sec_cm	41.750s	1.227ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	34.620s	2.035ms	50	50	100.00
		lc_ctrl_sec_cm	41.750s	1.227ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	34.620s	2.035ms	50	50	100.00
		lc_ctrl_sec_cm	41.750s	1.227ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	34.620s	2.035ms	50	50	100.00
		lc_ctrl_sec_cm	41.750s	1.227ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	18.200s	775.385us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.180s	146.329us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	37.550s	1.144ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	24.350s	837.100us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	24.350s	837.100us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	23.540s	4.505ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	22.740s	2.846ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	22.740s	2.846ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	38.541m	243.691ms	26	50	52.00
V3		TOTAL			26	50	52.00
		TOTAL			1005	1030	97.57

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.94	97.92	96.12	93.40	97.62	98.52	98.51	96.47

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:836) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 17 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 17 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.64853946405354642769193020538869383911180151909034014445378655608951648538382
      Line 7601, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 34713001302 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 34713001302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.lc_ctrl_stress_all_with_rand_reset.71726393931805979924581519509865426535452044929351575430767458611035773951365
      Line 20777, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 25561256606 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 25561256606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 15 more failures.

• UVM_ERROR (cip_base_vseq.sv:548) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 3 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 20.lc_ctrl_stress_all_with_rand_reset.35682878309943753940963934678403154240110160913087278520125839880727488714937
      Line 27132, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 79925471052 ps: (cip_base_vseq.sv:548) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 79925471052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 30.lc_ctrl_stress_all_with_rand_reset.24612692710219921234709410944540714493472328589867271925810272523020112874715
      Line 68746, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 243690921983 ps: (cip_base_vseq.sv:548) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 243690921983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 2.lc_ctrl_stress_all_with_rand_reset.69005892200906845558702296598744063253654459644521515291327186158497015461682
      Line 10484, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 122915077868 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 122915077868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 10.lc_ctrl_stress_all_with_rand_reset.30065611014781754721008888403087267664373951705188693279535811772493454211961
      Line 10707, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5350029078 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 5350029078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:548) [lc_ctrl_smoke_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_prog_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 33.lc_ctrl_stress_all_with_rand_reset.1069932889273000787190624073336146719942401866025720502136787797586658216779
      Line 30894, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 32714316141 ps: (cip_base_vseq.sv:548) [uvm_test_top.env.virtual_sequencer.lc_ctrl_smoke_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_prog_error fired unexpectedly!
        UVM_INFO @ 32714316141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:769) [lc_ctrl_lc_errors_vseq] Check failed otp_error_act == otp_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_errors has 1 failures.

    • 37.lc_ctrl_errors.18512403527663227372000429230171522668452670605253973929723901550315778441252
      Line 1866, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_errors/latest/run.log

        UVM_ERROR @ 482517854 ps: (lc_ctrl_errors_vseq.sv:769) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed otp_error_act == otp_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 482517854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 48.lc_ctrl_stress_all_with_rand_reset.84424093896499584909911417997834279304182544662234329291154593173873950200844
      Line 41254, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

Past Results

• Latest
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