LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Tuesday August 06 2024 23:02:29 UTC

GitHub Revision: 5fd4ecc0fc

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56304622830272859824235340993951659280265419461975949533183046575604373639200

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	11.380s	608.798us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.130s	16.293us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.100s	60.151us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.550s	226.041us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.790s	177.050us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.180s	95.676us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.100s	60.151us	20	20	100.00
		lc_ctrl_csr_aliasing	1.790s	177.050us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	12.490s	400.748us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	22.420s	652.130us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.990s	20.243us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	6.200s	581.445us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	36.220s	350.220us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	21.290s	818.227us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	36.220s	350.220us	50	50	100.00
		lc_ctrl_prog_failure	6.200s	581.445us	50	50	100.00
		lc_ctrl_errors	21.290s	818.227us	50	50	100.00
		lc_ctrl_security_escalation	18.800s	1.146ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.715m	19.618ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	27.580s	5.141ms	20	20	100.00
		lc_ctrl_jtag_errors	1.916m	18.531ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	12.210s	402.445us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	36.520s	6.996ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	27.580s	5.141ms	20	20	100.00
		lc_ctrl_jtag_errors	1.916m	18.531ms	20	20	100.00
		lc_ctrl_jtag_access	30.700s	1.341ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	39.420s	5.247ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.390s	446.599us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.080s	423.727us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	48.830s	40.414ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	18.510s	1.606ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.450s	105.354us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	7.190s	561.341us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.220s	290.539us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	41.350s	3.571ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.280s	22.292us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	12.665m	96.111ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.400s	50.639us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.930s	138.506us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.930s	138.506us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.130s	16.293us	5	5	100.00
		lc_ctrl_csr_rw	1.100s	60.151us	20	20	100.00
		lc_ctrl_csr_aliasing	1.790s	177.050us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.100s	169.987us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.130s	16.293us	5	5	100.00
		lc_ctrl_csr_rw	1.100s	60.151us	20	20	100.00
		lc_ctrl_csr_aliasing	1.790s	177.050us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.100s	169.987us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	38.400s	862.146us	5	5	100.00
		lc_ctrl_tl_intg_err	8.520s	1.356ms	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	8.520s	1.356ms	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	22.420s	652.130us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	36.220s	350.220us	50	50	100.00
		lc_ctrl_sec_cm	38.400s	862.146us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	36.220s	350.220us	50	50	100.00
		lc_ctrl_sec_cm	38.400s	862.146us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	36.220s	350.220us	50	50	100.00
		lc_ctrl_sec_cm	38.400s	862.146us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	36.220s	350.220us	50	50	100.00
		lc_ctrl_sec_cm	38.400s	862.146us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	36.220s	350.220us	50	50	100.00
		lc_ctrl_sec_cm	38.400s	862.146us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	36.220s	350.220us	50	50	100.00
		lc_ctrl_sec_cm	38.400s	862.146us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	36.220s	350.220us	50	50	100.00
		lc_ctrl_sec_cm	38.400s	862.146us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	36.220s	350.220us	50	50	100.00
		lc_ctrl_sec_cm	38.400s	862.146us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	18.800s	1.146ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	12.490s	400.748us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	36.520s	6.996ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	18.850s	1.501ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	18.850s	1.501ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	32.680s	5.443ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	17.960s	1.148ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	17.960s	1.148ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	54.470m	27.825ms	22	50	44.00
V3		TOTAL			22	50	44.00
		TOTAL			1002	1030	97.28

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.90	97.92	95.84	93.40	97.62	98.52	98.51	96.47

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:836) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 23 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.59563974164040110754848711872980642615516293984040796474558324797586772776288
      Line 14801, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 31938323334 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 31938323334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.lc_ctrl_stress_all_with_rand_reset.33694703065625222660030884544603963428408228207594565353973347485038709483670
      Line 20528, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 10123908090 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 10123908090 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 21 more failures.

• Error-[CNST-STOF] Constraint solver timeout failure has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 7.lc_ctrl_stress_all_with_rand_reset.40567283225180171635167382444095103088396863366453184540358501988042231004361
      Line 40097, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • 15.lc_ctrl_stress_all_with_rand_reset.6266587233717150620771241712733904794824996877552424261704721091799768718361
      Line 29390, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• UVM_ERROR (cip_base_scoreboard.sv:304) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 28.lc_ctrl_stress_all_with_rand_reset.11159602671637177905873118145184300863436942602489771233877242327516989643820
      Line 4614, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 14945855619 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 14945855619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 33.lc_ctrl_stress_all_with_rand_reset.80910200671789011724384195477219606357936167194339548782066009112363177450338
      Line 24293, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 21700425585 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 21700425585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:548) [lc_ctrl_smoke_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_prog_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 43.lc_ctrl_stress_all_with_rand_reset.72328593468126479386519798362852815695561701437084134080608232247027608688588
      Line 2904, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3337985426 ps: (cip_base_vseq.sv:548) [uvm_test_top.env.virtual_sequencer.lc_ctrl_smoke_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_prog_error fired unexpectedly!
        UVM_INFO @ 3337985426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.08.06_09.27.43
• 2024.08.05_10.55.53
• 2024.08.04_06.44.05
• 2024.08.03_08.55.03
• 2024.08.02_08.09.48
• 2024.08.01_09.35.26
• 2024.07.31_09.04.51