LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Wednesday August 07 2024 23:02:33 UTC

GitHub Revision: `bbf435ceff`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 6888687353677204195542416712589698377810102273194685652880785004967849651007

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	7.150s	594.865us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.160s	18.844us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.100s	15.694us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.990s	400.057us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.210s	55.461us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.510s	35.501us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.100s	15.694us	20	20	100.00
		lc_ctrl_csr_aliasing	1.210s	55.461us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	9.460s	794.035us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	14.040s	312.703us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.980s	12.729us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	6.330s	282.842us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	38.540s	1.508ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	21.480s	2.665ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	38.540s	1.508ms	50	50	100.00
		lc_ctrl_prog_failure	6.330s	282.842us	50	50	100.00
		lc_ctrl_errors	21.480s	2.665ms	50	50	100.00
		lc_ctrl_security_escalation	15.740s	451.663us	50	50	100.00
		lc_ctrl_jtag_state_failure	2.130m	4.273ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	18.210s	1.225ms	20	20	100.00
		lc_ctrl_jtag_errors	1.645m	3.702ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	17.460s	626.088us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	34.890s	3.853ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	18.210s	1.225ms	20	20	100.00
		lc_ctrl_jtag_errors	1.645m	3.702ms	20	20	100.00
		lc_ctrl_jtag_access	29.250s	2.609ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	31.530s	1.119ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	5.240s	941.990us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.440s	264.921us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	48.150s	2.196ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	16.280s	3.193ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.870s	170.656us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	2.690s	180.473us	10	10	100.00
		lc_ctrl_jtag_alert_test	4.110s	168.705us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	22.260s	3.609ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.260s	73.439us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	11.303m	24.371ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.270s	22.057us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.570s	608.609us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.570s	608.609us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.160s	18.844us	5	5	100.00
		lc_ctrl_csr_rw	1.100s	15.694us	20	20	100.00
		lc_ctrl_csr_aliasing	1.210s	55.461us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.150s	49.627us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.160s	18.844us	5	5	100.00
		lc_ctrl_csr_rw	1.100s	15.694us	20	20	100.00
		lc_ctrl_csr_aliasing	1.210s	55.461us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.150s	49.627us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	41.870s	1.277ms	5	5	100.00
		lc_ctrl_tl_intg_err	4.360s	118.550us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.360s	118.550us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	14.040s	312.703us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	38.540s	1.508ms	50	50	100.00
		lc_ctrl_sec_cm	41.870s	1.277ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	38.540s	1.508ms	50	50	100.00
		lc_ctrl_sec_cm	41.870s	1.277ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	38.540s	1.508ms	50	50	100.00
		lc_ctrl_sec_cm	41.870s	1.277ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	38.540s	1.508ms	50	50	100.00
		lc_ctrl_sec_cm	41.870s	1.277ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	38.540s	1.508ms	50	50	100.00
		lc_ctrl_sec_cm	41.870s	1.277ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	38.540s	1.508ms	50	50	100.00
		lc_ctrl_sec_cm	41.870s	1.277ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	38.540s	1.508ms	50	50	100.00
		lc_ctrl_sec_cm	41.870s	1.277ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	38.540s	1.508ms	50	50	100.00
		lc_ctrl_sec_cm	41.870s	1.277ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	15.740s	451.663us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	9.460s	794.035us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	34.890s	3.853ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	26.800s	1.262ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	26.800s	1.262ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	28.800s	1.263ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	19.590s	2.347ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	19.590s	2.347ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	41.986m	105.956ms	23	50	46.00
V3		TOTAL			23	50	46.00
		TOTAL			1002	1030	97.28

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.23	97.92	95.75	93.40	100.00	98.52	98.76	96.29

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:836) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 23 failures.
  - 2.lc_ctrl_stress_all_with_rand_reset.90113963336315976881977562439079010168809088317265863555994354614262229495481
    Line 11951, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 184322655109 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 184322655109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.lc_ctrl_stress_all_with_rand_reset.33953047101191791015944003325517990970376534868353424308492509602910224063048
    Line 326, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 177826217 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 177826217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 21 more failures.
UVM_ERROR (cip_base_scoreboard.sv:304) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 2 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 2 failures.
  - 9.lc_ctrl_stress_all_with_rand_reset.101573674636809668133044443325269122061673526719131527895861710298427988609372
    Line 10636, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 11369605151 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
  UVM_INFO @ 11369605151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 49.lc_ctrl_stress_all_with_rand_reset.68921986894902844113423085382334785711536670217553300855762701660368253304228
    Line 19811, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 12953731571 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
  UVM_INFO @ 12953731571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:548) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 10.lc_ctrl_stress_all_with_rand_reset.102392739382547594972988089855256118635480006345888280058567402068554531613058
    Line 37032, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 127827938787 ps: (cip_base_vseq.sv:548) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
  UVM_INFO @ 127827938787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:548) [lc_ctrl_regwen_during_op_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_prog_error fired unexpectedly! has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 37.lc_ctrl_stress_all_with_rand_reset.113425091468012976180405625570940177191536961616865084710530951025663847772043
    Line 24416, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 65429463584 ps: (cip_base_vseq.sv:548) [uvm_test_top.env.virtual_sequencer.lc_ctrl_regwen_during_op_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_prog_error fired unexpectedly!
  UVM_INFO @ 65429463584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:
- Test lc_ctrl_stress_all has 1 failures.
  - 39.lc_ctrl_stress_all.4928716912312959430201222078521812731154531389509305434877069737505942480305
    Line 2269, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_stress_all/latest/run.log
```
  UVM_ERROR @ 18717123229 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 18717123229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Wednesday August 07 2024 23:02:33 UTC

GitHub Revision: bbf435ceff

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 6888687353677204195542416712589698377810102273194685652880785004967849651007

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `bbf435ceff`