LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Thursday August 08 2024 23:02:08 UTC

GitHub Revision: 3707c48f56

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 96859198578252641766218135484681220968075710602306197013001824903089223290045

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	7.930s	962.234us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.260s	17.346us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.130s	15.374us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.940s	48.414us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.680s	67.015us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.910s	24.349us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.130s	15.374us	20	20	100.00
		lc_ctrl_csr_aliasing	1.680s	67.015us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	9.870s	95.175us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	26.290s	387.610us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.970s	12.311us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.500s	1.426ms	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	38.660s	373.785us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	20.610s	904.526us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	38.660s	373.785us	50	50	100.00
		lc_ctrl_prog_failure	4.500s	1.426ms	50	50	100.00
		lc_ctrl_errors	20.610s	904.526us	50	50	100.00
		lc_ctrl_security_escalation	14.720s	397.423us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.913m	8.002ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	16.900s	2.390ms	20	20	100.00
		lc_ctrl_jtag_errors	1.607m	14.964ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	15.530s	577.289us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	31.510s	1.957ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	16.900s	2.390ms	20	20	100.00
		lc_ctrl_jtag_errors	1.607m	14.964ms	20	20	100.00
		lc_ctrl_jtag_access	24.150s	1.052ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	35.190s	12.353ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	4.680s	714.983us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.440s	78.527us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	51.230s	41.377ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	23.000s	2.107ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.920s	43.549us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	6.580s	523.412us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.280s	65.690us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	27.390s	2.623ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.200s	20.977us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	8.967m	71.269ms	48	50	96.00
V2	alert_test	lc_ctrl_alert_test	1.560s	529.676us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.010s	741.826us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.010s	741.826us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.260s	17.346us	5	5	100.00
		lc_ctrl_csr_rw	1.130s	15.374us	20	20	100.00
		lc_ctrl_csr_aliasing	1.680s	67.015us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.940s	150.158us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.260s	17.346us	5	5	100.00
		lc_ctrl_csr_rw	1.130s	15.374us	20	20	100.00
		lc_ctrl_csr_aliasing	1.680s	67.015us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.940s	150.158us	20	20	100.00
V2		TOTAL			698	700	99.71
V2S	tl_intg_err	lc_ctrl_sec_cm	37.240s	232.172us	5	5	100.00
		lc_ctrl_tl_intg_err	4.380s	528.227us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.380s	528.227us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	26.290s	387.610us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	38.660s	373.785us	50	50	100.00
		lc_ctrl_sec_cm	37.240s	232.172us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	38.660s	373.785us	50	50	100.00
		lc_ctrl_sec_cm	37.240s	232.172us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	38.660s	373.785us	50	50	100.00
		lc_ctrl_sec_cm	37.240s	232.172us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	38.660s	373.785us	50	50	100.00
		lc_ctrl_sec_cm	37.240s	232.172us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	38.660s	373.785us	50	50	100.00
		lc_ctrl_sec_cm	37.240s	232.172us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	38.660s	373.785us	50	50	100.00
		lc_ctrl_sec_cm	37.240s	232.172us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	38.660s	373.785us	50	50	100.00
		lc_ctrl_sec_cm	37.240s	232.172us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	38.660s	373.785us	50	50	100.00
		lc_ctrl_sec_cm	37.240s	232.172us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	14.720s	397.423us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	9.870s	95.175us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	31.510s	1.957ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	24.480s	706.772us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	24.480s	706.772us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	25.910s	1.071ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	21.420s	706.022us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	21.420s	706.022us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.474h	201.506ms	24	50	48.00
V3		TOTAL			24	50	48.00
		TOTAL			1002	1030	97.28

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.24	97.92	96.03	93.40	100.00	98.52	98.51	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:836) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 19 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 19 failures.

    • 3.lc_ctrl_stress_all_with_rand_reset.97604424486507019719484622203316941429706093334056358623715988932727938894557
      Line 17493, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 11807896372 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 11807896372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 7.lc_ctrl_stress_all_with_rand_reset.83944344184721266491808981433352309222687548292264548634524850459339868559363
      Line 18956, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 38220893623 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 38220893623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 17 more failures.

• UVM_ERROR (cip_base_vseq.sv:548) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 3 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 2.lc_ctrl_stress_all_with_rand_reset.77413818791378960262493994343891484237640416890809784853526702830442093973145
      Line 15774, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3590920547 ps: (cip_base_vseq.sv:548) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 3590920547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 28.lc_ctrl_stress_all_with_rand_reset.58790595022786826320108191419549939740097284836451150439239074158964901160998
      Line 33884, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 86496676162 ps: (cip_base_vseq.sv:548) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 86496676162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• Error-[CNST-STOF] Constraint solver timeout failure has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 6.lc_ctrl_stress_all_with_rand_reset.105469873771938597933206143387801378866727881881334789562255297130105882792712
      Line 47249, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • 17.lc_ctrl_stress_all_with_rand_reset.79878983612369702959209455721815087970841273421186532560271118498751850993080
      Line 59743, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• UVM_ERROR (cip_base_scoreboard.sv:304) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 14.lc_ctrl_stress_all_with_rand_reset.94135148807662317924238635544429720090819441796050404257055260809588734188680
      Line 8249, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 13522642580 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 13522642580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 21.lc_ctrl_stress_all_with_rand_reset.38206021597376596756202746090276011587809081454689409057718768806186341593426
      Line 8799, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3421114937 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 3421114937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 2 failures:

  • Test lc_ctrl_stress_all has 2 failures.

    • 22.lc_ctrl_stress_all.82789354763236915896095714018110246783461799024183561739099793859807569920200
      Line 17942, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 26789227122 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 26789227122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 35.lc_ctrl_stress_all.84342417773666073507872053599090556304119264692649388199238547962188027198722
      Line 2195, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 128573147 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 128573147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.08.08_09.02.48
• 2024.08.07_08.55.46
• 2024.08.06_09.27.43
• 2024.08.05_10.55.53
• 2024.08.04_06.44.05
• 2024.08.03_08.55.03
• 2024.08.02_08.09.48