LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Friday August 09 2024 23:02:07 UTC

GitHub Revision: 07b417ef03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 39866585070056138360117926942905553094756411441088058786676399955088054585836

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	13.810s	293.901us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.120s	18.395us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.060s	29.332us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.350s	55.840us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.410s	26.916us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.800s	31.932us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.060s	29.332us	20	20	100.00
		lc_ctrl_csr_aliasing	1.410s	26.916us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.940s	243.993us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	27.340s	1.607ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.970s	12.871us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.770s	855.701us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	38.960s	615.709us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	17.840s	1.791ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	38.960s	615.709us	50	50	100.00
		lc_ctrl_prog_failure	5.770s	855.701us	50	50	100.00
		lc_ctrl_errors	17.840s	1.791ms	50	50	100.00
		lc_ctrl_security_escalation	16.000s	416.816us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.862m	13.530ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	15.650s	2.160ms	20	20	100.00
		lc_ctrl_jtag_errors	1.087m	4.096ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	15.430s	3.470ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	27.290s	1.502ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	15.650s	2.160ms	20	20	100.00
		lc_ctrl_jtag_errors	1.087m	4.096ms	20	20	100.00
		lc_ctrl_jtag_access	18.990s	8.054ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	37.580s	5.442ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.360s	271.055us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.280s	386.634us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	42.870s	1.799ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	12.870s	671.808us	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.870s	38.185us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.910s	2.516ms	10	10	100.00
		lc_ctrl_jtag_alert_test	3.550s	489.194us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	21.400s	1.707ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.190s	52.490us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	16.134m	135.016ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.350s	23.850us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	6.340s	160.501us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	6.340s	160.501us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.120s	18.395us	5	5	100.00
		lc_ctrl_csr_rw	1.060s	29.332us	20	20	100.00
		lc_ctrl_csr_aliasing	1.410s	26.916us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.050s	182.512us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.120s	18.395us	5	5	100.00
		lc_ctrl_csr_rw	1.060s	29.332us	20	20	100.00
		lc_ctrl_csr_aliasing	1.410s	26.916us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.050s	182.512us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	39.890s	844.225us	5	5	100.00
		lc_ctrl_tl_intg_err	4.460s	250.373us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.460s	250.373us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	27.340s	1.607ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	38.960s	615.709us	50	50	100.00
		lc_ctrl_sec_cm	39.890s	844.225us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	38.960s	615.709us	50	50	100.00
		lc_ctrl_sec_cm	39.890s	844.225us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	38.960s	615.709us	50	50	100.00
		lc_ctrl_sec_cm	39.890s	844.225us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	38.960s	615.709us	50	50	100.00
		lc_ctrl_sec_cm	39.890s	844.225us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	38.960s	615.709us	50	50	100.00
		lc_ctrl_sec_cm	39.890s	844.225us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	38.960s	615.709us	50	50	100.00
		lc_ctrl_sec_cm	39.890s	844.225us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	38.960s	615.709us	50	50	100.00
		lc_ctrl_sec_cm	39.890s	844.225us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	38.960s	615.709us	50	50	100.00
		lc_ctrl_sec_cm	39.890s	844.225us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	16.000s	416.816us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.940s	243.993us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	27.290s	1.502ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	21.510s	1.199ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	21.510s	1.199ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	27.160s	1.415ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	16.330s	3.371ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	16.330s	3.371ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	31.338m	51.413ms	29	50	58.00
V3		TOTAL			29	50	58.00
		TOTAL			1009	1030	97.96

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.20	97.92	95.75	93.40	100.00	98.52	98.51	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:836) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 16 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 16 failures.

    • 2.lc_ctrl_stress_all_with_rand_reset.13671817607790521428813473742541371192624494256175282146987335231930075340779
      Line 40261, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 108358748355 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 108358748355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 8.lc_ctrl_stress_all_with_rand_reset.109140399685166824349263263655323577192608553123617477224427929669199609426306
      Line 34693, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 24634850405 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 24634850405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 14 more failures.

• Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 9.lc_ctrl_stress_all_with_rand_reset.75277688295742033503405387369010850605525728270545711269656664094593517757396
      Line 33160, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 16.lc_ctrl_stress_all_with_rand_reset.37656770292042712657718319270607722605613222537729897084370997427625532616204
      Line 15323, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 97723897582 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 97723897582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:304) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 18.lc_ctrl_stress_all_with_rand_reset.114058733678554314120765166671488817197558186493882282467703915777711609526531
      Line 4589, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6232153934 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 6232153934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:548) [lc_ctrl_regwen_during_op_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_prog_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 32.lc_ctrl_stress_all_with_rand_reset.45326973769182226825950938467062279302798748924396420559720152999677535514954
      Line 23196, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 84643210820 ps: (cip_base_vseq.sv:548) [uvm_test_top.env.virtual_sequencer.lc_ctrl_regwen_during_op_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_prog_error fired unexpectedly!
        UVM_INFO @ 84643210820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:548) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 48.lc_ctrl_stress_all_with_rand_reset.108125726722343001515107169836926384609902053695679424337023028893150848573585
      Line 39796, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 142968837007 ps: (cip_base_vseq.sv:548) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 142968837007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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• 2024.08.09_07.50.33
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