LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Saturday August 10 2024 23:02:23 UTC

GitHub Revision: `07b417ef03`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2196818177928134427831197337249851347498377272679561983541244979366753055772

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	10.730s	688.404us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.170s	107.858us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.190s	17.893us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.010s	181.343us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.800s	95.589us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.060s	27.411us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.190s	17.893us	20	20	100.00
		lc_ctrl_csr_aliasing	1.800s	95.589us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	9.980s	115.870us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	23.760s	744.055us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.900s	40.131us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.420s	89.024us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	42.180s	382.968us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	21.860s	891.558us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	42.180s	382.968us	50	50	100.00
		lc_ctrl_prog_failure	4.420s	89.024us	50	50	100.00
		lc_ctrl_errors	21.860s	891.558us	50	50	100.00
		lc_ctrl_security_escalation	15.740s	1.176ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.724m	2.765ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	15.020s	1.836ms	20	20	100.00
		lc_ctrl_jtag_errors	1.106m	2.238ms	19	20	95.00
V2	jtag_access	lc_ctrl_jtag_smoke	13.980s	2.344ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	28.930s	823.192us	20	20	100.00
		lc_ctrl_jtag_prog_failure	15.020s	1.836ms	20	20	100.00
		lc_ctrl_jtag_errors	1.106m	2.238ms	19	20	95.00
		lc_ctrl_jtag_access	28.180s	3.965ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	38.020s	1.346ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	2.710s	405.902us	10	10	100.00
		lc_ctrl_jtag_csr_rw	4.080s	311.491us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	35.320s	6.219ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	13.530s	519.081us	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.480s	26.100us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	6.510s	1.413ms	10	10	100.00
		lc_ctrl_jtag_alert_test	2.090s	115.594us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	31.370s	2.736ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.330s	18.937us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	7.954m	13.795ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.300s	95.007us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.700s	116.291us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.700s	116.291us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.170s	107.858us	5	5	100.00
		lc_ctrl_csr_rw	1.190s	17.893us	20	20	100.00
		lc_ctrl_csr_aliasing	1.800s	95.589us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.800s	40.568us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.170s	107.858us	5	5	100.00
		lc_ctrl_csr_rw	1.190s	17.893us	20	20	100.00
		lc_ctrl_csr_aliasing	1.800s	95.589us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.800s	40.568us	20	20	100.00
V2		TOTAL			698	700	99.71
V2S	tl_intg_err	lc_ctrl_sec_cm	44.490s	1.244ms	5	5	100.00
		lc_ctrl_tl_intg_err	4.600s	492.101us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.600s	492.101us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	23.760s	744.055us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	42.180s	382.968us	50	50	100.00
		lc_ctrl_sec_cm	44.490s	1.244ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	42.180s	382.968us	50	50	100.00
		lc_ctrl_sec_cm	44.490s	1.244ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	42.180s	382.968us	50	50	100.00
		lc_ctrl_sec_cm	44.490s	1.244ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	42.180s	382.968us	50	50	100.00
		lc_ctrl_sec_cm	44.490s	1.244ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	42.180s	382.968us	50	50	100.00
		lc_ctrl_sec_cm	44.490s	1.244ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	42.180s	382.968us	50	50	100.00
		lc_ctrl_sec_cm	44.490s	1.244ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	42.180s	382.968us	50	50	100.00
		lc_ctrl_sec_cm	44.490s	1.244ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	42.180s	382.968us	50	50	100.00
		lc_ctrl_sec_cm	44.490s	1.244ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	15.740s	1.176ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	9.980s	115.870us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	28.930s	823.192us	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	21.090s	491.757us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	21.090s	491.757us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	23.410s	695.672us	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	23.200s	2.717ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	23.200s	2.717ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	41.966m	944.447ms	26	50	52.00
V3		TOTAL			26	50	52.00
		TOTAL			1004	1030	97.48

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	25	92.59
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.79	97.92	95.29	93.40	97.62	98.52	98.51	96.29

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:836) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 18 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 18 failures.
  - 0.lc_ctrl_stress_all_with_rand_reset.52564536654745632280350961975871950617873800850663747576901797177841408929766
    Line 39802, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 105463792142 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 105463792142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.lc_ctrl_stress_all_with_rand_reset.62144922424076467131255645221708686877422146289505952906631257102297232494171
    Line 48592, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 169379466050 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 169379466050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 16 more failures.
Error-[CNST-STOF] Constraint solver timeout failure has 2 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 2 failures.
  - 38.lc_ctrl_stress_all_with_rand_reset.17883017836811184679832962524216287181056424730916526137531745982256274111111
    Line 37454, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Error-[CNST-STOF] Constraint solver timeout failure
  ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
    Exceeded cpu time limit during solve.
    Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
    limit.  The default cpu limit is 1000 seconds per partition.
```
  - 44.lc_ctrl_stress_all_with_rand_reset.16547348203934415007187267149463362129792516503052703907021352425074492997358
    Line 38745, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Error-[CNST-STOF] Constraint solver timeout failure
  ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
    Exceeded cpu time limit during solve.
    Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
    limit.  The default cpu limit is 1000 seconds per partition.
```
UVM_ERROR (cip_base_scoreboard.sv:304) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 2 failures:
- Test lc_ctrl_stress_all has 1 failures.
  - 41.lc_ctrl_stress_all.74905657065168946784754524636001982197707774308817631912220073788596402307807
    Line 13691, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_stress_all/latest/run.log
```
  UVM_ERROR @ 4694431528 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
  UVM_INFO @ 4694431528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 42.lc_ctrl_stress_all_with_rand_reset.100215781419001800062025101901383837405200876105540502230099387724595065149823
    Line 42122, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 43817121636 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
  UVM_INFO @ 43817121636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:
- Test lc_ctrl_jtag_errors has 1 failures.
  - 4.lc_ctrl_jtag_errors.6763468240924430419043791551852723543178283812379117492934963659737802166914
    Line 1997, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_errors/latest/run.log
```
  UVM_ERROR @ 1788177426 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1788177426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:548) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 8.lc_ctrl_stress_all_with_rand_reset.87397654073328044939347111981247653118927161867048662870087169910097588937319
    Line 11043, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4508439175 ps: (cip_base_vseq.sv:548) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
  UVM_INFO @ 4508439175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:548) [lc_ctrl_regwen_during_op_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_prog_error fired unexpectedly! has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 21.lc_ctrl_stress_all_with_rand_reset.80831270739458308154885786836908764039586616360907757319816992125656224101187
    Line 2338, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3169617396 ps: (cip_base_vseq.sv:548) [uvm_test_top.env.virtual_sequencer.lc_ctrl_regwen_during_op_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_prog_error fired unexpectedly!
  UVM_INFO @ 3169617396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (lc_ctrl_scoreboard.sv:238) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestUnlocked* has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 48.lc_ctrl_stress_all_with_rand_reset.85272040202918250561966428953630716298515614106881634088331070752090258623550
    Line 2351, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 20596156478 ps: (lc_ctrl_scoreboard.sv:238) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (5 [0x5] vs 10 [0xa]) Called from line: 100, LC_St DecLcStTestUnlocked2
  UVM_INFO @ 20596156478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Saturday August 10 2024 23:02:23 UTC

GitHub Revision: 07b417ef03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2196818177928134427831197337249851347498377272679561983541244979366753055772

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `07b417ef03`