LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Sunday August 11 2024 23:02:21 UTC

GitHub Revision: 07b417ef03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 6142445146730822936893044599112392910298048088673599708943858624824800218011

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	12.440s	858.009us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.240s	18.013us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.130s	16.467us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.940s	307.188us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.400s	26.015us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.200s	165.261us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.130s	16.467us	20	20	100.00
		lc_ctrl_csr_aliasing	1.400s	26.015us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	9.890s	649.717us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	27.110s	390.492us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.020s	12.686us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.600s	185.748us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	36.180s	281.408us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	24.000s	3.777ms	49	50	98.00
V2	security_escalation	lc_ctrl_state_failure	36.180s	281.408us	50	50	100.00
		lc_ctrl_prog_failure	4.600s	185.748us	50	50	100.00
		lc_ctrl_errors	24.000s	3.777ms	49	50	98.00
		lc_ctrl_security_escalation	19.110s	4.460ms	50	50	100.00
		lc_ctrl_jtag_state_failure	2.150m	8.500ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	16.500s	558.772us	20	20	100.00
		lc_ctrl_jtag_errors	2.164m	16.481ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	17.820s	1.467ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	26.680s	6.330ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	16.500s	558.772us	20	20	100.00
		lc_ctrl_jtag_errors	2.164m	16.481ms	20	20	100.00
		lc_ctrl_jtag_access	34.760s	8.635ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	28.200s	2.126ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	6.610s	556.463us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.560s	316.545us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	23.620s	959.226us	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	16.670s	2.416ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.740s	74.931us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	6.260s	1.003ms	10	10	100.00
		lc_ctrl_jtag_alert_test	2.100s	88.218us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	16.300s	701.183us	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.280s	20.896us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	11.366m	18.160ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.830s	54.006us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.690s	123.101us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.690s	123.101us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.240s	18.013us	5	5	100.00
		lc_ctrl_csr_rw	1.130s	16.467us	20	20	100.00
		lc_ctrl_csr_aliasing	1.400s	26.015us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.860s	67.772us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.240s	18.013us	5	5	100.00
		lc_ctrl_csr_rw	1.130s	16.467us	20	20	100.00
		lc_ctrl_csr_aliasing	1.400s	26.015us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.860s	67.772us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	44.370s	1.033ms	5	5	100.00
		lc_ctrl_tl_intg_err	4.340s	110.153us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.340s	110.153us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	27.110s	390.492us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	36.180s	281.408us	50	50	100.00
		lc_ctrl_sec_cm	44.370s	1.033ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	36.180s	281.408us	50	50	100.00
		lc_ctrl_sec_cm	44.370s	1.033ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	36.180s	281.408us	50	50	100.00
		lc_ctrl_sec_cm	44.370s	1.033ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	36.180s	281.408us	50	50	100.00
		lc_ctrl_sec_cm	44.370s	1.033ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	36.180s	281.408us	50	50	100.00
		lc_ctrl_sec_cm	44.370s	1.033ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	36.180s	281.408us	50	50	100.00
		lc_ctrl_sec_cm	44.370s	1.033ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	36.180s	281.408us	50	50	100.00
		lc_ctrl_sec_cm	44.370s	1.033ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	36.180s	281.408us	50	50	100.00
		lc_ctrl_sec_cm	44.370s	1.033ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	19.110s	4.460ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	9.890s	649.717us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	26.680s	6.330ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	31.870s	4.927ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	31.870s	4.927ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	27.080s	4.525ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	18.590s	506.214us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	18.590s	506.214us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	50.824m	372.172ms	23	50	46.00
V3		TOTAL			23	50	46.00
		TOTAL			1002	1030	97.28

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.82	97.92	95.47	93.40	97.62	98.52	98.51	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:836) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 21 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 21 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.26379943345803584276533067884315931574257105397650158103598769600491387274730
      Line 3346, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2579948629 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2579948629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.lc_ctrl_stress_all_with_rand_reset.68116334291365298658987810790969326690344676385094152511650079757242174482178
      Line 57731, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 122043143058 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 122043143058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 19 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:304) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 3 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 5.lc_ctrl_stress_all_with_rand_reset.99283684576881763497082761672196603623623589477347732095688387384899432029049
      Line 44082, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 146848920677 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 146848920677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 11.lc_ctrl_stress_all_with_rand_reset.9582669899520262412707166064721507083591716583004988876756875040240021791060
      Line 32519, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 25778129393 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 25778129393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• Error-[CNST-STOF] Constraint solver timeout failure has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 42.lc_ctrl_stress_all_with_rand_reset.63584917261675572258970882878448837601922191884150053940887463979755838672797
      Line 44090, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • 48.lc_ctrl_stress_all_with_rand_reset.38351319536522418937100243692985882692621578429304877375551828462928049501368
      Line 29408, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_errors has 1 failures.

    • 6.lc_ctrl_errors.49311967895716883574322994872246069392996081150143918381106600391157870714420
      Line 338, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_errors/latest/run.log

        UVM_ERROR @  26558812 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @  26558812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:548) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 8.lc_ctrl_stress_all_with_rand_reset.51374949125985359436977156800463559058871612319099155192095220507561171612304
      Line 14557, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 90326970215 ps: (cip_base_vseq.sv:548) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 90326970215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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