LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Monday August 12 2024 23:02:30 UTC

GitHub Revision: c082b8981f

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107262934208806092150901079363789224644653433402469901409990667510497383888850

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	13.740s	949.427us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.240s	37.174us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.150s	18.359us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.770s	177.360us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.210s	65.262us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.140s	27.969us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.150s	18.359us	20	20	100.00
		lc_ctrl_csr_aliasing	1.210s	65.262us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.080s	91.301us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	22.470s	1.471ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.990s	14.574us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.870s	207.695us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	35.280s	4.844ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	19.410s	1.191ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	35.280s	4.844ms	50	50	100.00
		lc_ctrl_prog_failure	5.870s	207.695us	50	50	100.00
		lc_ctrl_errors	19.410s	1.191ms	50	50	100.00
		lc_ctrl_security_escalation	17.840s	2.137ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.759m	3.155ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	27.800s	2.139ms	20	20	100.00
		lc_ctrl_jtag_errors	2.249m	55.496ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	8.090s	980.462us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	35.380s	1.183ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	27.800s	2.139ms	20	20	100.00
		lc_ctrl_jtag_errors	2.249m	55.496ms	20	20	100.00
		lc_ctrl_jtag_access	27.330s	1.424ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	34.440s	8.815ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.510s	1.880ms	10	10	100.00
		lc_ctrl_jtag_csr_rw	5.180s	368.558us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	43.870s	8.909ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	25.410s	6.128ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.070s	49.093us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	5.070s	724.617us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.030s	119.966us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	44.670s	7.646ms	9	10	90.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.150s	17.560us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	10.182m	78.322ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.370s	23.110us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.880s	185.870us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.880s	185.870us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.240s	37.174us	5	5	100.00
		lc_ctrl_csr_rw	1.150s	18.359us	20	20	100.00
		lc_ctrl_csr_aliasing	1.210s	65.262us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.930s	141.790us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.240s	37.174us	5	5	100.00
		lc_ctrl_csr_rw	1.150s	18.359us	20	20	100.00
		lc_ctrl_csr_aliasing	1.210s	65.262us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.930s	141.790us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	41.480s	573.661us	5	5	100.00
		lc_ctrl_tl_intg_err	4.270s	126.463us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.270s	126.463us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	22.470s	1.471ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	35.280s	4.844ms	50	50	100.00
		lc_ctrl_sec_cm	41.480s	573.661us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	35.280s	4.844ms	50	50	100.00
		lc_ctrl_sec_cm	41.480s	573.661us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	35.280s	4.844ms	50	50	100.00
		lc_ctrl_sec_cm	41.480s	573.661us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	35.280s	4.844ms	50	50	100.00
		lc_ctrl_sec_cm	41.480s	573.661us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	35.280s	4.844ms	50	50	100.00
		lc_ctrl_sec_cm	41.480s	573.661us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	35.280s	4.844ms	50	50	100.00
		lc_ctrl_sec_cm	41.480s	573.661us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	35.280s	4.844ms	50	50	100.00
		lc_ctrl_sec_cm	41.480s	573.661us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	35.280s	4.844ms	50	50	100.00
		lc_ctrl_sec_cm	41.480s	573.661us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	17.840s	2.137ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.080s	91.301us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	35.380s	1.183ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	19.150s	848.973us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	19.150s	848.973us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	28.990s	2.306ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	23.160s	751.548us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	23.160s	751.548us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	2.791m	19.763ms	21	50	42.00
V3		TOTAL			21	50	42.00
		TOTAL			1000	1030	97.09

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.11	97.92	95.29	93.40	100.00	98.52	98.51	96.11

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:848) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 24 failures.

    • 3.lc_ctrl_stress_all_with_rand_reset.78136092337298846791674905270899270782730781757814796101682801463693813201832
      Line 9008, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 972652036 ps: (cip_base_vseq.sv:848) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 972652036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 6.lc_ctrl_stress_all_with_rand_reset.25341816370417346108757721000367836136279892055044369409166352187918445684455
      Line 7355, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1565700804 ps: (cip_base_vseq.sv:848) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1565700804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 22 more failures.

• UVM_ERROR (cip_base_vseq.sv:556) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 3 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 11.lc_ctrl_stress_all_with_rand_reset.98702140001293212351693003533756377668826291724340862913239522852696457093866
      Line 6063, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 9042818672 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 9042818672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 20.lc_ctrl_stress_all_with_rand_reset.115293744866920502516057920286104001793079916152879691114753977007031418105791
      Line 991, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5491260239 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 5491260239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_FATAL (lc_ctrl_jtag_priority_vseq.sv:135) [lc_ctrl_jtag_priority_vseq] wait for simultaneous mutex claim has 1 failures:

  • Test lc_ctrl_jtag_priority has 1 failures.

    • 3.lc_ctrl_jtag_priority.55291906813987245556601620071476752554034310807291995042339930451391335570201
      Line 595, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_priority/latest/run.log

        UVM_FATAL @ 22846944765 ps: (lc_ctrl_jtag_priority_vseq.sv:135) [uvm_test_top.env.virtual_sequencer.lc_ctrl_jtag_priority_vseq] wait for simultaneous mutex claim
        UVM_INFO @ 22846944765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_scoreboard.sv:243) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestLocked* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 7.lc_ctrl_stress_all_with_rand_reset.6854839297150011960896603321008898940802360903897379562117060802717890945506
      Line 1216, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1713588704 ps: (lc_ctrl_scoreboard.sv:243) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (10 [0xa] vs 5 [0x5]) Called from line: 100, LC_St DecLcStTestLocked6
        UVM_INFO @ 1713588704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_scoreboard.sv:243) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStRma has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 45.lc_ctrl_stress_all_with_rand_reset.26566408693676669413441771839215322557593893729128507558155112880269414734074
      Line 4149, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1162755787 ps: (lc_ctrl_scoreboard.sv:243) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (10 [0xa] vs 5 [0x5]) Called from line: 100, LC_St DecLcStRma
        UVM_INFO @ 1162755787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.08.12_08.29.33
• 2024.08.11_08.15.23
• 2024.08.10_08.19.01
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