LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Tuesday August 13 2024 23:04:47 UTC

GitHub Revision: 098010d125

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 12185085088694708177096441863424670920996379189869351644310607217057882846251

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	11.900s	216.229us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.240s	67.021us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.200s	18.889us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.760s	72.593us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.300s	178.120us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.990s	31.384us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.200s	18.889us	20	20	100.00
		lc_ctrl_csr_aliasing	1.300s	178.120us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	11.680s	461.524us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	20.340s	353.094us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.030s	13.402us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	6.210s	168.780us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	39.380s	264.838us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	22.490s	563.737us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	39.380s	264.838us	50	50	100.00
		lc_ctrl_prog_failure	6.210s	168.780us	50	50	100.00
		lc_ctrl_errors	22.490s	563.737us	50	50	100.00
		lc_ctrl_security_escalation	17.950s	2.535ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.877m	6.124ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	19.660s	1.235ms	20	20	100.00
		lc_ctrl_jtag_errors	1.410m	27.747ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	13.260s	3.362ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	37.120s	1.104ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	19.660s	1.235ms	20	20	100.00
		lc_ctrl_jtag_errors	1.410m	27.747ms	20	20	100.00
		lc_ctrl_jtag_access	31.900s	1.917ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	35.830s	5.016ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.910s	147.245us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.320s	275.446us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	38.510s	18.110ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	15.950s	1.480ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.850s	40.247us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	3.760s	118.602us	10	10	100.00
		lc_ctrl_jtag_alert_test	3.970s	796.500us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	46.620s	4.186ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.300s	81.473us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	10.071m	31.510ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.510s	42.828us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.620s	137.166us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.620s	137.166us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.240s	67.021us	5	5	100.00
		lc_ctrl_csr_rw	1.200s	18.889us	20	20	100.00
		lc_ctrl_csr_aliasing	1.300s	178.120us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.640s	43.381us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.240s	67.021us	5	5	100.00
		lc_ctrl_csr_rw	1.200s	18.889us	20	20	100.00
		lc_ctrl_csr_aliasing	1.300s	178.120us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.640s	43.381us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	38.600s	218.600us	5	5	100.00
		lc_ctrl_tl_intg_err	3.710s	194.125us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	3.710s	194.125us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	20.340s	353.094us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	39.380s	264.838us	50	50	100.00
		lc_ctrl_sec_cm	38.600s	218.600us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	39.380s	264.838us	50	50	100.00
		lc_ctrl_sec_cm	38.600s	218.600us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	39.380s	264.838us	50	50	100.00
		lc_ctrl_sec_cm	38.600s	218.600us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	39.380s	264.838us	50	50	100.00
		lc_ctrl_sec_cm	38.600s	218.600us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	39.380s	264.838us	50	50	100.00
		lc_ctrl_sec_cm	38.600s	218.600us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	39.380s	264.838us	50	50	100.00
		lc_ctrl_sec_cm	38.600s	218.600us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	39.380s	264.838us	50	50	100.00
		lc_ctrl_sec_cm	38.600s	218.600us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	39.380s	264.838us	50	50	100.00
		lc_ctrl_sec_cm	38.600s	218.600us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	17.950s	2.535ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.680s	461.524us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	37.120s	1.104ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	20.930s	1.096ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	20.930s	1.096ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	27.170s	3.070ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	16.820s	16.647ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	16.820s	16.647ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	4.039m	6.885ms	24	50	48.00
V3		TOTAL			24	50	48.00
		TOTAL			1004	1030	97.48

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.16	97.92	95.47	93.40	100.00	98.52	98.51	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:867) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 22 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 22 failures.

    • 2.lc_ctrl_stress_all_with_rand_reset.8377844723065597483618313487840900825656354697359788548303430224049209314911
      Line 4939, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 64739826868 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 64739826868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.lc_ctrl_stress_all_with_rand_reset.94228490943893116322588240986634410380049022025492613183454334763535628322517
      Line 325, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 105181126 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 105181126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 20 more failures.

• UVM_ERROR (cip_base_vseq.sv:556) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 3 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.22840537248091399691276893009459773192249212459738826157428794675759103546119
      Line 2637, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1356260523 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 1356260523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 17.lc_ctrl_stress_all_with_rand_reset.32814196125220065178176744031954438624499973822464443205198659764701213095634
      Line 5231, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 952039543 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 952039543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR (lc_ctrl_scoreboard.sv:238) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestUnlocked* has 1 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 8.lc_ctrl_stress_all_with_rand_reset.107373577888007933738641952563315526739820128095313412307209901278083156252798
      Line 10013, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 9252935807 ps: (lc_ctrl_scoreboard.sv:238) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (5 [0x5] vs 10 [0xa]) Called from line: 100, LC_St DecLcStTestUnlocked2
        UVM_INFO @ 9252935807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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• 2024.08.13_07.59.21
• 2024.08.12_08.29.33
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