LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Wednesday August 14 2024 23:02:33 UTC

GitHub Revision: 584c3d46af

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 75916000169703078066460267353397937307391759551032957123310220571514951708138

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	6.730s	155.799us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.290s	16.808us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.110s	16.899us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.580s	256.044us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.640s	303.006us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.850s	48.597us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.110s	16.899us	20	20	100.00
		lc_ctrl_csr_aliasing	1.640s	303.006us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	11.400s	1.648ms	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	21.110s	2.749ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.880s	11.880us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.910s	191.768us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	40.880s	1.177ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	24.780s	701.860us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	40.880s	1.177ms	50	50	100.00
		lc_ctrl_prog_failure	4.910s	191.768us	50	50	100.00
		lc_ctrl_errors	24.780s	701.860us	50	50	100.00
		lc_ctrl_security_escalation	16.130s	3.890ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.442m	9.756ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	19.930s	2.640ms	20	20	100.00
		lc_ctrl_jtag_errors	1.075m	8.726ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	15.520s	1.165ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	31.920s	4.431ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	19.930s	2.640ms	20	20	100.00
		lc_ctrl_jtag_errors	1.075m	8.726ms	20	20	100.00
		lc_ctrl_jtag_access	32.050s	8.840ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	40.550s	5.808ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	5.260s	462.783us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.080s	421.535us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	26.590s	1.100ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	24.140s	1.032ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.180s	49.261us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.580s	161.192us	10	10	100.00
		lc_ctrl_jtag_alert_test	3.230s	1.118ms	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	21.020s	821.393us	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.220s	19.445us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	7.355m	24.473ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.370s	58.340us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.220s	145.717us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.220s	145.717us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.290s	16.808us	5	5	100.00
		lc_ctrl_csr_rw	1.110s	16.899us	20	20	100.00
		lc_ctrl_csr_aliasing	1.640s	303.006us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.010s	169.371us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.290s	16.808us	5	5	100.00
		lc_ctrl_csr_rw	1.110s	16.899us	20	20	100.00
		lc_ctrl_csr_aliasing	1.640s	303.006us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.010s	169.371us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	40.120s	1.077ms	5	5	100.00
		lc_ctrl_tl_intg_err	4.190s	197.337us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.190s	197.337us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	21.110s	2.749ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	40.880s	1.177ms	50	50	100.00
		lc_ctrl_sec_cm	40.120s	1.077ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	40.880s	1.177ms	50	50	100.00
		lc_ctrl_sec_cm	40.120s	1.077ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	40.880s	1.177ms	50	50	100.00
		lc_ctrl_sec_cm	40.120s	1.077ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	40.880s	1.177ms	50	50	100.00
		lc_ctrl_sec_cm	40.120s	1.077ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	40.880s	1.177ms	50	50	100.00
		lc_ctrl_sec_cm	40.120s	1.077ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	40.880s	1.177ms	50	50	100.00
		lc_ctrl_sec_cm	40.120s	1.077ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	40.880s	1.177ms	50	50	100.00
		lc_ctrl_sec_cm	40.120s	1.077ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	40.880s	1.177ms	50	50	100.00
		lc_ctrl_sec_cm	40.120s	1.077ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	16.130s	3.890ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.400s	1.648ms	50	50	100.00
		lc_ctrl_jtag_state_post_trans	31.920s	4.431ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	18.610s	851.461us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	18.610s	851.461us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	24.930s	774.960us	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	16.300s	5.881ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	16.300s	5.881ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	3.010m	5.651ms	21	50	42.00
V3		TOTAL			21	50	42.00
		TOTAL			1000	1030	97.09

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.95	97.92	96.12	93.40	97.62	98.52	98.76	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:867) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 27 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 27 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.3832935206290056114194637966904389395775394428097574865682638350069266430413
      Line 2780, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 15981249055 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 15981249055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.lc_ctrl_stress_all_with_rand_reset.82723469969954096602185618619496634100988146122513805643420631177432088856784
      Line 368, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 110690435 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 110690435 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 25 more failures.

• UVM_ERROR (cip_base_vseq.sv:556) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 6.lc_ctrl_stress_all_with_rand_reset.114424579701493446143073800014654135964576663860851169393657522946962492909996
      Line 6689, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 47887604789 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 47887604789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 7.lc_ctrl_stress_all_with_rand_reset.81256426679764400029687370361093844031379955213520106161525603487516644241546
      Line 5543, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2284622877 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 2284622877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_stress_all has 1 failures.

    • 38.lc_ctrl_stress_all.38289803534303877612310206252207158368456451593490770714629244472333031742551
      Line 12427, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 24473442922 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 24473442922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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