LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Thursday August 15 2024 23:02:21 UTC

GitHub Revision: `d09e282b26`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 47908880312501934977153450267828796412449789719488445881682136509150457490963

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	8.590s	426.920us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.220s	39.395us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.150s	20.332us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.980s	163.346us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.620s	36.624us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.750s	86.105us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.150s	20.332us	20	20	100.00
		lc_ctrl_csr_aliasing	1.620s	36.624us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.070s	99.761us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	21.040s	697.583us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.950s	71.275us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.890s	456.817us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	34.820s	260.266us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	26.100s	765.444us	49	50	98.00
V2	security_escalation	lc_ctrl_state_failure	34.820s	260.266us	50	50	100.00
		lc_ctrl_prog_failure	4.890s	456.817us	50	50	100.00
		lc_ctrl_errors	26.100s	765.444us	49	50	98.00
		lc_ctrl_security_escalation	19.260s	2.001ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.629m	12.898ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	16.740s	553.068us	20	20	100.00
		lc_ctrl_jtag_errors	1.541m	21.082ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	16.650s	1.345ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	25.180s	2.733ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	16.740s	553.068us	20	20	100.00
		lc_ctrl_jtag_errors	1.541m	21.082ms	20	20	100.00
		lc_ctrl_jtag_access	26.140s	1.134ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	36.610s	10.508ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.220s	110.067us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.780s	287.178us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	24.210s	2.359ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	15.430s	2.556ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.930s	181.950us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	8.070s	314.470us	10	10	100.00
		lc_ctrl_jtag_alert_test	3.150s	631.255us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	46.650s	2.046ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.150s	15.670us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	13.935m	98.049ms	46	50	92.00
V2	alert_test	lc_ctrl_alert_test	1.320s	51.955us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.100s	654.469us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.100s	654.469us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.220s	39.395us	5	5	100.00
		lc_ctrl_csr_rw	1.150s	20.332us	20	20	100.00
		lc_ctrl_csr_aliasing	1.620s	36.624us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.960s	50.052us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.220s	39.395us	5	5	100.00
		lc_ctrl_csr_rw	1.150s	20.332us	20	20	100.00
		lc_ctrl_csr_aliasing	1.620s	36.624us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.960s	50.052us	20	20	100.00
V2		TOTAL			695	700	99.29
V2S	tl_intg_err	lc_ctrl_sec_cm	40.050s	483.410us	5	5	100.00
		lc_ctrl_tl_intg_err	5.110s	188.580us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	5.110s	188.580us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	21.040s	697.583us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	34.820s	260.266us	50	50	100.00
		lc_ctrl_sec_cm	40.050s	483.410us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	34.820s	260.266us	50	50	100.00
		lc_ctrl_sec_cm	40.050s	483.410us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	34.820s	260.266us	50	50	100.00
		lc_ctrl_sec_cm	40.050s	483.410us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	34.820s	260.266us	50	50	100.00
		lc_ctrl_sec_cm	40.050s	483.410us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	34.820s	260.266us	50	50	100.00
		lc_ctrl_sec_cm	40.050s	483.410us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	34.820s	260.266us	50	50	100.00
		lc_ctrl_sec_cm	40.050s	483.410us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	34.820s	260.266us	50	50	100.00
		lc_ctrl_sec_cm	40.050s	483.410us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	34.820s	260.266us	50	50	100.00
		lc_ctrl_sec_cm	40.050s	483.410us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	19.260s	2.001ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.070s	99.761us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	25.180s	2.733ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	28.410s	797.063us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	28.410s	797.063us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	21.990s	2.054ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	16.360s	1.967ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	16.360s	1.967ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	2.824m	3.897ms	25	50	50.00
V3		TOTAL			25	50	50.00
		TOTAL			1000	1030	97.09

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	25	92.59
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.86	97.92	95.93	93.40	97.62	98.52	98.51	96.11

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 21 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 21 failures.
  - 4.lc_ctrl_stress_all_with_rand_reset.63928007792108440678840458311864642696350624354738987978896063386989582680593
    Line 335, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8457179779 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 8457179779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.lc_ctrl_stress_all_with_rand_reset.49903218112768999500712296213018951237581607045104132426602129130904576901683
    Line 1975, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4496074363 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4496074363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 19 more failures.
UVM_ERROR (cip_base_scoreboard.sv:304) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 3 failures:
- Test lc_ctrl_stress_all has 3 failures.
  - 2.lc_ctrl_stress_all.84470652239693309942487340567635057921334993732193806289176967249096566702447
    Line 3377, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all/latest/run.log
```
  UVM_ERROR @ 18282108428 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
  UVM_INFO @ 18282108428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 18.lc_ctrl_stress_all.56615886927593466054596007082645342101295446052389499904348042293013857722111
    Line 2977, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_stress_all/latest/run.log
```
  UVM_ERROR @ 55622005882 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
  UVM_INFO @ 55622005882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 2 failures:
- Test lc_ctrl_errors has 1 failures.
  - 28.lc_ctrl_errors.76370732611433356052581677248375653880149928903388643534095463741202169017604
    Line 1828, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_errors/latest/run.log
```
  UVM_ERROR @ 495429629 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 495429629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test lc_ctrl_stress_all has 1 failures.
  - 33.lc_ctrl_stress_all.61245645977014388978219036611433677884106590728200702999476311756989522019323
    Line 14544, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_stress_all/latest/run.log
```
  UVM_ERROR @ 7105141173 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 7105141173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (lc_ctrl_scoreboard.sv:243) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestLocked* has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 5.lc_ctrl_stress_all_with_rand_reset.24893447619398545556597776278643342947249668708081655724807029656437553548232
    Line 5112, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 638296283 ps: (lc_ctrl_scoreboard.sv:243) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (10 [0xa] vs 5 [0x5]) Called from line: 100, LC_St DecLcStTestLocked1
  UVM_INFO @ 638296283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:556) [lc_ctrl_smoke_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_prog_error fired unexpectedly! has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 7.lc_ctrl_stress_all_with_rand_reset.22119071295421257717410719756155957940131818954961736230783358985989291332313
    Line 1338, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2174722561 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_smoke_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_prog_error fired unexpectedly!
  UVM_INFO @ 2174722561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (lc_ctrl_scoreboard.sv:238) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStRma has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 21.lc_ctrl_stress_all_with_rand_reset.46533767094228926459576828165022667054759801792807622729050839087041291173861
    Line 3662, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1446557707 ps: (lc_ctrl_scoreboard.sv:238) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (5 [0x5] vs 10 [0xa]) Called from line: 100, LC_St DecLcStRma
  UVM_INFO @ 1446557707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (lc_ctrl_scoreboard.sv:238) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestUnlocked* has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 45.lc_ctrl_stress_all_with_rand_reset.7874647252449379890140842940571599383256299413559763404246718989388208194899
    Line 1216, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 850654933 ps: (lc_ctrl_scoreboard.sv:238) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (5 [0x5] vs 10 [0xa]) Called from line: 100, LC_St DecLcStTestUnlocked5
  UVM_INFO @ 850654933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Thursday August 15 2024 23:02:21 UTC

GitHub Revision: d09e282b26

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 47908880312501934977153450267828796412449789719488445881682136509150457490963

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `d09e282b26`