LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Friday August 16 2024 23:02:10 UTC

GitHub Revision: 76588857da

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107397868712693014844033025164446565408841343499325418676943424680076749785789

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	5.190s	97.116us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.180s	15.020us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.110s	15.761us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.750s	125.647us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.820s	73.680us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.240s	31.658us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.110s	15.761us	20	20	100.00
		lc_ctrl_csr_aliasing	1.820s	73.680us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	9.890s	293.408us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	17.580s	1.251ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.000s	12.768us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.820s	120.383us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	39.710s	436.320us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	21.160s	745.383us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	39.710s	436.320us	50	50	100.00
		lc_ctrl_prog_failure	4.820s	120.383us	50	50	100.00
		lc_ctrl_errors	21.160s	745.383us	50	50	100.00
		lc_ctrl_security_escalation	16.240s	432.650us	50	50	100.00
		lc_ctrl_jtag_state_failure	2.068m	16.328ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	15.370s	2.354ms	20	20	100.00
		lc_ctrl_jtag_errors	1.652m	14.717ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	17.710s	3.165ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	31.960s	9.622ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	15.370s	2.354ms	20	20	100.00
		lc_ctrl_jtag_errors	1.652m	14.717ms	20	20	100.00
		lc_ctrl_jtag_access	31.630s	5.643ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	33.120s	5.036ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	4.450s	765.493us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.540s	1.071ms	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	31.060s	1.380ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	9.560s	2.254ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.040s	165.361us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.250s	184.275us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.330s	79.041us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	40.690s	1.790ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.110s	13.946us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	7.470m	56.832ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.360s	110.322us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	3.740s	408.513us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	3.740s	408.513us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.180s	15.020us	5	5	100.00
		lc_ctrl_csr_rw	1.110s	15.761us	20	20	100.00
		lc_ctrl_csr_aliasing	1.820s	73.680us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.760s	68.869us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.180s	15.020us	5	5	100.00
		lc_ctrl_csr_rw	1.110s	15.761us	20	20	100.00
		lc_ctrl_csr_aliasing	1.820s	73.680us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.760s	68.869us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	40.760s	415.186us	5	5	100.00
		lc_ctrl_tl_intg_err	5.510s	737.465us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	5.510s	737.465us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	17.580s	1.251ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	39.710s	436.320us	50	50	100.00
		lc_ctrl_sec_cm	40.760s	415.186us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	39.710s	436.320us	50	50	100.00
		lc_ctrl_sec_cm	40.760s	415.186us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	39.710s	436.320us	50	50	100.00
		lc_ctrl_sec_cm	40.760s	415.186us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	39.710s	436.320us	50	50	100.00
		lc_ctrl_sec_cm	40.760s	415.186us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	39.710s	436.320us	50	50	100.00
		lc_ctrl_sec_cm	40.760s	415.186us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	39.710s	436.320us	50	50	100.00
		lc_ctrl_sec_cm	40.760s	415.186us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	39.710s	436.320us	50	50	100.00
		lc_ctrl_sec_cm	40.760s	415.186us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	39.710s	436.320us	50	50	100.00
		lc_ctrl_sec_cm	40.760s	415.186us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	16.240s	432.650us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	9.890s	293.408us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	31.960s	9.622ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	22.660s	571.924us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	22.660s	571.924us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	24.890s	2.676ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	14.400s	800.625us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	14.400s	800.625us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	3.105m	4.106ms	23	50	46.00
V3		TOTAL			23	50	46.00
		TOTAL			1002	1030	97.28

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.60	97.97	95.84	93.40	95.24	98.73	98.76	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:867) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 22 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 22 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.5335169506951322533104418391531952761196047170310576095882191051218945933942
      Line 326, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 265617983 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 265617983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.lc_ctrl_stress_all_with_rand_reset.58784122739902726070283977549478291380349182545244946646902665476419604798119
      Line 6645, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5945105857 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 5945105857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 20 more failures.

• UVM_ERROR (cip_base_vseq.sv:556) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 4 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 4 failures.

    • 8.lc_ctrl_stress_all_with_rand_reset.41284783029669436811138783903605595660269562494803967164605903801528607691006
      Line 4108, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1060004982 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 1060004982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 33.lc_ctrl_stress_all_with_rand_reset.79468171215152368970222076393897026696214639952439770103407090833077767647909
      Line 4232, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2074944167 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 2074944167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 2 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:304) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:

  • Test lc_ctrl_stress_all has 1 failures.

    • 18.lc_ctrl_stress_all.93812238094773071345183408452641420076887066054222544830075343649416909009736
      Line 4608, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 4234158038 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 4234158038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_scoreboard.sv:238) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestUnlocked* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 26.lc_ctrl_stress_all_with_rand_reset.48758094054695649140077583197999373634296726003115167511695611232512327060571
      Line 566, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 312489492 ps: (lc_ctrl_scoreboard.sv:238) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (5 [0x5] vs 10 [0xa]) Called from line: 100, LC_St DecLcStTestUnlocked4
        UVM_INFO @ 312489492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.08.16_08.34.01
• 2024.08.15_05.27.42
• 2024.08.14_08.31.25
• 2024.08.13_07.59.21
• 2024.08.12_08.29.33
• 2024.08.11_08.15.23
• 2024.08.10_08.19.01