LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Saturday August 17 2024 23:02:17 UTC

GitHub Revision: 76588857da

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 94235727392619910305578226901221990521512464990339520078429467885466612377995

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	7.980s	297.563us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.170s	30.823us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.070s	15.275us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.860s	355.235us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.330s	25.444us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.760s	467.031us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.070s	15.275us	20	20	100.00
		lc_ctrl_csr_aliasing	1.330s	25.444us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	11.080s	196.224us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	19.370s	294.432us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.970s	13.878us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.710s	114.608us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	37.270s	1.052ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	26.100s	1.478ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	37.270s	1.052ms	50	50	100.00
		lc_ctrl_prog_failure	4.710s	114.608us	50	50	100.00
		lc_ctrl_errors	26.100s	1.478ms	50	50	100.00
		lc_ctrl_security_escalation	16.760s	1.755ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.413m	2.541ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	14.110s	4.087ms	20	20	100.00
		lc_ctrl_jtag_errors	2.226m	20.324ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	15.120s	2.291ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	30.630s	1.770ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	14.110s	4.087ms	20	20	100.00
		lc_ctrl_jtag_errors	2.226m	20.324ms	20	20	100.00
		lc_ctrl_jtag_access	25.550s	2.251ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	39.600s	6.272ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	6.500s	264.989us	10	10	100.00
		lc_ctrl_jtag_csr_rw	4.710s	182.900us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	51.960s	4.663ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	16.510s	1.466ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.990s	193.161us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.340s	140.146us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.490s	163.436us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	49.810s	2.234ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.210s	71.625us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	9.249m	14.025ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.250s	23.263us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.230s	203.727us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.230s	203.727us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.170s	30.823us	5	5	100.00
		lc_ctrl_csr_rw	1.070s	15.275us	20	20	100.00
		lc_ctrl_csr_aliasing	1.330s	25.444us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.930s	181.493us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.170s	30.823us	5	5	100.00
		lc_ctrl_csr_rw	1.070s	15.275us	20	20	100.00
		lc_ctrl_csr_aliasing	1.330s	25.444us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.930s	181.493us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	37.730s	461.657us	5	5	100.00
		lc_ctrl_tl_intg_err	4.290s	213.439us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.290s	213.439us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	19.370s	294.432us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	37.270s	1.052ms	50	50	100.00
		lc_ctrl_sec_cm	37.730s	461.657us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	37.270s	1.052ms	50	50	100.00
		lc_ctrl_sec_cm	37.730s	461.657us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	37.270s	1.052ms	50	50	100.00
		lc_ctrl_sec_cm	37.730s	461.657us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	37.270s	1.052ms	50	50	100.00
		lc_ctrl_sec_cm	37.730s	461.657us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	37.270s	1.052ms	50	50	100.00
		lc_ctrl_sec_cm	37.730s	461.657us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	37.270s	1.052ms	50	50	100.00
		lc_ctrl_sec_cm	37.730s	461.657us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	37.270s	1.052ms	50	50	100.00
		lc_ctrl_sec_cm	37.730s	461.657us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	37.270s	1.052ms	50	50	100.00
		lc_ctrl_sec_cm	37.730s	461.657us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	16.760s	1.755ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.080s	196.224us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	30.630s	1.770ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	23.150s	1.247ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	23.150s	1.247ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	26.960s	5.442ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	14.070s	367.128us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	14.070s	367.128us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.909m	13.213ms	22	50	44.00
V3		TOTAL			22	50	44.00
		TOTAL			1002	1030	97.28

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.21	97.92	95.75	93.40	100.00	98.52	98.76	96.11

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:867) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 25 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 25 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.66108932149065701368326077462768720380795730811848403002058034916614607357163
      Line 1566, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3717583317 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3717583317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.lc_ctrl_stress_all_with_rand_reset.5644921986548134430926276428650699293549337893495241862337097209506370551138
      Line 370, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 229315275 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 229315275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 23 more failures.

• UVM_ERROR (cip_base_vseq.sv:556) [lc_ctrl_smoke_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_prog_error fired unexpectedly! has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 21.lc_ctrl_stress_all_with_rand_reset.113643271367305175090432821665251248434293002587008084517429695188468910775109
      Line 7312, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 26938925742 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_smoke_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_prog_error fired unexpectedly!
        UVM_INFO @ 26938925742 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 48.lc_ctrl_stress_all_with_rand_reset.65757668124121945874006999026475644767583643369436633343895668313491730913613
      Line 9087, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2024502686 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_smoke_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_prog_error fired unexpectedly!
        UVM_INFO @ 2024502686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_scoreboard.sv:243) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestLocked* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 15.lc_ctrl_stress_all_with_rand_reset.14307165927802558334776357933949523022128999376462144811634405888071123026137
      Line 4044, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2385477195 ps: (lc_ctrl_scoreboard.sv:243) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (10 [0xa] vs 5 [0x5]) Called from line: 100, LC_St DecLcStTestLocked4
        UVM_INFO @ 2385477195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.08.17_07.12.39
• 2024.08.16_08.34.01
• 2024.08.15_05.27.42
• 2024.08.14_08.31.25
• 2024.08.13_07.59.21
• 2024.08.12_08.29.33
• 2024.08.11_08.15.23