LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Sunday August 18 2024 23:02:23 UTC

GitHub Revision: f1535c5540

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29514139809134543525249635699831421949407409612590789671953066019961489233719

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	11.420s	386.189us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.270s	19.083us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.200s	30.903us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.070s	51.647us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.280s	76.009us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.040s	86.699us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.200s	30.903us	20	20	100.00
		lc_ctrl_csr_aliasing	1.280s	76.009us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	12.150s	167.003us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	27.500s	427.794us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.060s	13.620us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	6.220s	295.240us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	38.200s	319.571us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	24.620s	2.471ms	49	50	98.00
V2	security_escalation	lc_ctrl_state_failure	38.200s	319.571us	50	50	100.00
		lc_ctrl_prog_failure	6.220s	295.240us	50	50	100.00
		lc_ctrl_errors	24.620s	2.471ms	49	50	98.00
		lc_ctrl_security_escalation	15.380s	750.374us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.719m	3.128ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	17.910s	4.858ms	20	20	100.00
		lc_ctrl_jtag_errors	1.528m	3.291ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	15.840s	9.930ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	21.690s	1.246ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	17.910s	4.858ms	20	20	100.00
		lc_ctrl_jtag_errors	1.528m	3.291ms	20	20	100.00
		lc_ctrl_jtag_access	29.190s	1.325ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	37.750s	2.536ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	5.200s	211.484us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.710s	91.710us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	25.920s	3.048ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	20.740s	15.468ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.020s	37.540us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	6.730s	4.214ms	10	10	100.00
		lc_ctrl_jtag_alert_test	2.050s	866.996us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	13.540s	7.056ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.340s	22.519us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	15.860m	27.539ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.320s	97.041us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.720s	151.793us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.720s	151.793us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.270s	19.083us	5	5	100.00
		lc_ctrl_csr_rw	1.200s	30.903us	20	20	100.00
		lc_ctrl_csr_aliasing	1.280s	76.009us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.890s	41.247us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.270s	19.083us	5	5	100.00
		lc_ctrl_csr_rw	1.200s	30.903us	20	20	100.00
		lc_ctrl_csr_aliasing	1.280s	76.009us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.890s	41.247us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	41.360s	217.833us	5	5	100.00
		lc_ctrl_tl_intg_err	6.020s	218.955us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	6.020s	218.955us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	27.500s	427.794us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	38.200s	319.571us	50	50	100.00
		lc_ctrl_sec_cm	41.360s	217.833us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	38.200s	319.571us	50	50	100.00
		lc_ctrl_sec_cm	41.360s	217.833us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	38.200s	319.571us	50	50	100.00
		lc_ctrl_sec_cm	41.360s	217.833us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	38.200s	319.571us	50	50	100.00
		lc_ctrl_sec_cm	41.360s	217.833us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	38.200s	319.571us	50	50	100.00
		lc_ctrl_sec_cm	41.360s	217.833us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	38.200s	319.571us	50	50	100.00
		lc_ctrl_sec_cm	41.360s	217.833us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	38.200s	319.571us	50	50	100.00
		lc_ctrl_sec_cm	41.360s	217.833us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	38.200s	319.571us	50	50	100.00
		lc_ctrl_sec_cm	41.360s	217.833us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	15.380s	750.374us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	12.150s	167.003us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	21.690s	1.246ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	21.890s	4.369ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	21.890s	4.369ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	30.320s	4.497ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	24.030s	752.560us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	24.030s	752.560us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	3.748m	20.927ms	28	50	56.00
V3		TOTAL			28	50	56.00
		TOTAL			1007	1030	97.77

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.21	97.92	95.75	93.40	100.00	98.52	98.76	96.11

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:867) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 20 failures.

    • 2.lc_ctrl_stress_all_with_rand_reset.67956143121474758562304850946484706066545509760734516888195225872727124997081
      Line 336, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 951979250 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 951979250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.lc_ctrl_stress_all_with_rand_reset.40079062875937908316108140823845526927893993118549940101153506625074811397759
      Line 371, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 454085262 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 454085262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 18 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_errors has 1 failures.

    • 26.lc_ctrl_errors.88856586179774251307076838700477300437471096387583042020070219215786113439774
      Line 1605, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_errors/latest/run.log

        UVM_ERROR @ 112403872 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 112403872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:771) [lc_ctrl_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 28.lc_ctrl_stress_all_with_rand_reset.8772161455487319859160363150547528532613171856023931027664546194349256451516
      Line 5356, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5152539527 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 5152539527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:556) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 35.lc_ctrl_stress_all_with_rand_reset.85405428730487467048556913850922215231241882190580537110514598936102198923998
      Line 2389, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2371061145 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 2371061145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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