LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Monday August 19 2024 23:02:17 UTC

GitHub Revision: e45ccd274a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 28901767565311589526059483176077826609560752276120463932311122284088110669824

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	9.470s	738.602us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.260s	19.503us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.150s	17.691us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	3.320s	742.728us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.290s	65.986us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.770s	34.371us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.150s	17.691us	20	20	100.00
		lc_ctrl_csr_aliasing	1.290s	65.986us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.690s	148.779us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	19.440s	2.676ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.000s	12.915us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	6.820s	244.521us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	40.290s	1.304ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	21.190s	524.744us	49	50	98.00
V2	security_escalation	lc_ctrl_state_failure	40.290s	1.304ms	50	50	100.00
		lc_ctrl_prog_failure	6.820s	244.521us	50	50	100.00
		lc_ctrl_errors	21.190s	524.744us	49	50	98.00
		lc_ctrl_security_escalation	17.630s	3.701ms	50	50	100.00
		lc_ctrl_jtag_state_failure	2.063m	15.486ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	18.770s	2.521ms	20	20	100.00
		lc_ctrl_jtag_errors	1.233m	5.650ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	14.760s	569.743us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	30.810s	2.144ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	18.770s	2.521ms	20	20	100.00
		lc_ctrl_jtag_errors	1.233m	5.650ms	20	20	100.00
		lc_ctrl_jtag_access	19.730s	881.740us	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	39.920s	17.017ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	5.570s	231.364us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.340s	65.835us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	31.520s	2.626ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	11.620s	482.923us	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.080s	51.449us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.680s	1.099ms	10	10	100.00
		lc_ctrl_jtag_alert_test	2.300s	130.351us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	11.060s	15.353ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.100s	15.269us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	12.140m	23.020ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.430s	88.983us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.910s	257.445us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.910s	257.445us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.260s	19.503us	5	5	100.00
		lc_ctrl_csr_rw	1.150s	17.691us	20	20	100.00
		lc_ctrl_csr_aliasing	1.290s	65.986us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.920s	44.698us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.260s	19.503us	5	5	100.00
		lc_ctrl_csr_rw	1.150s	17.691us	20	20	100.00
		lc_ctrl_csr_aliasing	1.290s	65.986us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.920s	44.698us	20	20	100.00
V2		TOTAL			698	700	99.71
V2S	tl_intg_err	lc_ctrl_sec_cm	36.240s	943.669us	5	5	100.00
		lc_ctrl_tl_intg_err	4.080s	520.084us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.080s	520.084us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	19.440s	2.676ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	40.290s	1.304ms	50	50	100.00
		lc_ctrl_sec_cm	36.240s	943.669us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	40.290s	1.304ms	50	50	100.00
		lc_ctrl_sec_cm	36.240s	943.669us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	40.290s	1.304ms	50	50	100.00
		lc_ctrl_sec_cm	36.240s	943.669us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	40.290s	1.304ms	50	50	100.00
		lc_ctrl_sec_cm	36.240s	943.669us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	40.290s	1.304ms	50	50	100.00
		lc_ctrl_sec_cm	36.240s	943.669us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	40.290s	1.304ms	50	50	100.00
		lc_ctrl_sec_cm	36.240s	943.669us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	40.290s	1.304ms	50	50	100.00
		lc_ctrl_sec_cm	36.240s	943.669us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	40.290s	1.304ms	50	50	100.00
		lc_ctrl_sec_cm	36.240s	943.669us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	17.630s	3.701ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.690s	148.779us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	30.810s	2.144ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	18.500s	613.344us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	18.500s	613.344us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	23.640s	1.087ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	13.510s	380.761us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	13.510s	380.761us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	3.211m	3.941ms	21	50	42.00
V3		TOTAL			21	50	42.00
		TOTAL			999	1030	96.99

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	25	92.59
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.82	97.92	95.66	93.40	97.62	98.31	98.76	96.11

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:867) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 27 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 27 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.49499609882197726382052700677414293062770511714362301814668949927644781328689
      Line 326, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 105305204 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 105305204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.lc_ctrl_stress_all_with_rand_reset.74758154228715885815912287172192946093049973052273033104422414378622762420017
      Line 1560, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3630274558 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3630274558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 25 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 2 failures:

  • Test lc_ctrl_errors has 1 failures.

    • 37.lc_ctrl_errors.11599683640078177894377672715454414529487116642885319813001781723907073120869
      Line 2121, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_errors/latest/run.log

        UVM_ERROR @ 594629707 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 594629707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 40.lc_ctrl_stress_all_with_rand_reset.58393342826120600723543977761553260615465394308172536851529038879192190956162
      Line 5852, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4317254323 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 4317254323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:304) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:

  • Test lc_ctrl_stress_all has 1 failures.

    • 17.lc_ctrl_stress_all.98487168725538481955590386953490455536832302228618682030181026522979479636618
      Line 999, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 2265639723 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 2265639723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:556) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 32.lc_ctrl_stress_all_with_rand_reset.112545985346870840968193200568311529550002651324514366345877212269462112438461
      Line 2800, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 8988576371 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 8988576371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.08.19_08.05.57
• 2024.08.18_08.34.35
• 2024.08.17_07.12.39
• 2024.08.16_08.34.01
• 2024.08.15_05.27.42
• 2024.08.14_08.31.25
• 2024.08.13_07.59.21