LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Wednesday August 21 2024 01:12:47 UTC

GitHub Revision: 34b8fc33e3

Branch: earlgrey_1_0_0_2024_08_20_RC0

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 77645589415139663032322841827996135987237190720163469870959218015679941996572

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	7.590s	108.080us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.440s	72.614us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.460s	13.204us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.910s	246.923us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.870s	668.365us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.110s	564.498us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.460s	13.204us	20	20	100.00
		lc_ctrl_csr_aliasing	1.870s	668.365us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	14.010s	97.742us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	21.990s	1.482ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.370s	11.251us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	6.070s	668.028us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	37.490s	698.115us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	18.940s	772.222us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	37.490s	698.115us	50	50	100.00
		lc_ctrl_prog_failure	6.070s	668.028us	50	50	100.00
		lc_ctrl_errors	18.940s	772.222us	50	50	100.00
		lc_ctrl_security_escalation	15.790s	1.564ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.516m	2.492ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	18.180s	2.084ms	20	20	100.00
		lc_ctrl_jtag_errors	1.222m	3.071ms	19	20	95.00
V2	jtag_access	lc_ctrl_jtag_smoke	10.700s	1.807ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	28.320s	2.189ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	18.180s	2.084ms	20	20	100.00
		lc_ctrl_jtag_errors	1.222m	3.071ms	19	20	95.00
		lc_ctrl_jtag_access	24.810s	4.561ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	31.110s	2.369ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.600s	958.510us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.300s	66.304us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	45.580s	2.749ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	22.650s	1.092ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.160s	41.776us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	6.790s	237.536us	10	10	100.00
		lc_ctrl_jtag_alert_test	3.030s	275.553us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	24.440s	3.919ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	2.180s	27.835us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	15.279m	65.614ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	2.100s	161.092us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.090s	132.269us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.090s	132.269us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.440s	72.614us	5	5	100.00
		lc_ctrl_csr_rw	1.460s	13.204us	20	20	100.00
		lc_ctrl_csr_aliasing	1.870s	668.365us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.400s	90.970us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.440s	72.614us	5	5	100.00
		lc_ctrl_csr_rw	1.460s	13.204us	20	20	100.00
		lc_ctrl_csr_aliasing	1.870s	668.365us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.400s	90.970us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	32.590s	443.240us	5	5	100.00
		lc_ctrl_tl_intg_err	3.960s	112.315us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	3.960s	112.315us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	21.990s	1.482ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	37.490s	698.115us	50	50	100.00
		lc_ctrl_sec_cm	32.590s	443.240us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	37.490s	698.115us	50	50	100.00
		lc_ctrl_sec_cm	32.590s	443.240us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	37.490s	698.115us	50	50	100.00
		lc_ctrl_sec_cm	32.590s	443.240us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	37.490s	698.115us	50	50	100.00
		lc_ctrl_sec_cm	32.590s	443.240us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	37.490s	698.115us	50	50	100.00
		lc_ctrl_sec_cm	32.590s	443.240us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	37.490s	698.115us	50	50	100.00
		lc_ctrl_sec_cm	32.590s	443.240us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	37.490s	698.115us	50	50	100.00
		lc_ctrl_sec_cm	32.590s	443.240us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	37.490s	698.115us	50	50	100.00
		lc_ctrl_sec_cm	32.590s	443.240us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	15.790s	1.564ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	14.010s	97.742us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	28.320s	2.189ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	27.110s	849.519us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	27.110s	849.519us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	23.790s	1.045ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	25.420s	807.581us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	25.420s	807.581us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	2.646m	4.782ms	21	50	42.00
V3		TOTAL			21	50	42.00
		TOTAL			1000	1030	97.09

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.84	97.92	95.56	93.40	97.62	98.52	98.76	96.11

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:867) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 26 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 26 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.6065830797927010445517767693603122878387146364894497045855550804927698994308
      Line 1501, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5218099509 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 5218099509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.lc_ctrl_stress_all_with_rand_reset.67829862150206860679509219796263297654038796220927089488684245020956653885166
      Line 1738, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 14582579908 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 14582579908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 24 more failures.

• UVM_ERROR (lc_ctrl_scoreboard.sv:243) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestLocked* has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 25.lc_ctrl_stress_all_with_rand_reset.81076491580369074374972666923733837111448031589234346777093453819563652303888
      Line 1638, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6523863795 ps: (lc_ctrl_scoreboard.sv:243) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (10 [0xa] vs 5 [0x5]) Called from line: 100, LC_St DecLcStTestLocked5
        UVM_INFO @ 6523863795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 46.lc_ctrl_stress_all_with_rand_reset.60806395646534890226339956473276559843434020563535628090005648648303937225560
      Line 4471, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2826293797 ps: (lc_ctrl_scoreboard.sv:243) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (10 [0xa] vs 5 [0x5]) Called from line: 100, LC_St DecLcStTestLocked5
        UVM_INFO @ 2826293797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_jtag_errors has 1 failures.

    • 4.lc_ctrl_jtag_errors.82994895397435066086620836886539816647733308242513063686069731533622448109284
      Line 3467, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_errors/latest/run.log

        UVM_ERROR @ 1287570003 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 1287570003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:556) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 20.lc_ctrl_stress_all_with_rand_reset.97340737991441099910272620390074866771791648294503709613564193242580956759925
      Line 1848, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 11342838028 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 11342838028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.08.20_07.52.13
• 2024.08.19_08.05.57
• 2024.08.18_08.34.35
• 2024.08.17_07.12.39
• 2024.08.16_08.34.01
• 2024.08.15_05.27.42
• 2024.08.14_08.31.25