LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Thursday August 22 2024 22:02:20 UTC

GitHub Revision: `0825c81be0`

Branch: os_regression_2024_08_22

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 102736032995262985039236458937944411119924968439319752111682827040046827694889

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	7.910s	165.605us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.040s	35.781us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	0.950s	45.888us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.580s	241.064us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.460s	34.377us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.840s	28.439us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	0.950s	45.888us	20	20	100.00
		lc_ctrl_csr_aliasing	1.460s	34.377us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	11.620s	88.241us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	18.260s	1.542ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.900s	13.583us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.420s	157.654us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	35.890s	954.116us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	17.680s	3.488ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	35.890s	954.116us	50	50	100.00
		lc_ctrl_prog_failure	5.420s	157.654us	50	50	100.00
		lc_ctrl_errors	17.680s	3.488ms	50	50	100.00
		lc_ctrl_security_escalation	13.670s	2.654ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.928m	16.676ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	23.320s	1.013ms	20	20	100.00
		lc_ctrl_jtag_errors	1.464m	5.922ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	11.930s	477.472us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	25.570s	1.409ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	23.320s	1.013ms	20	20	100.00
		lc_ctrl_jtag_errors	1.464m	5.922ms	20	20	100.00
		lc_ctrl_jtag_access	18.780s	6.214ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	25.220s	4.015ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	4.490s	241.021us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.480s	534.513us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	43.120s	11.124ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	23.410s	4.744ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.390s	125.844us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	3.070s	176.448us	10	10	100.00
		lc_ctrl_jtag_alert_test	3.920s	1.054ms	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	8.460s	1.564ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.050s	36.374us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	8.116m	18.248ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.170s	24.296us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.060s	404.363us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.060s	404.363us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.040s	35.781us	5	5	100.00
		lc_ctrl_csr_rw	0.950s	45.888us	20	20	100.00
		lc_ctrl_csr_aliasing	1.460s	34.377us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.790s	115.620us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.040s	35.781us	5	5	100.00
		lc_ctrl_csr_rw	0.950s	45.888us	20	20	100.00
		lc_ctrl_csr_aliasing	1.460s	34.377us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.790s	115.620us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	40.760s	911.851us	5	5	100.00
		lc_ctrl_tl_intg_err	4.500s	597.021us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.500s	597.021us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	18.260s	1.542ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	35.890s	954.116us	50	50	100.00
		lc_ctrl_sec_cm	40.760s	911.851us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	35.890s	954.116us	50	50	100.00
		lc_ctrl_sec_cm	40.760s	911.851us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	35.890s	954.116us	50	50	100.00
		lc_ctrl_sec_cm	40.760s	911.851us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	35.890s	954.116us	50	50	100.00
		lc_ctrl_sec_cm	40.760s	911.851us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	35.890s	954.116us	50	50	100.00
		lc_ctrl_sec_cm	40.760s	911.851us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	35.890s	954.116us	50	50	100.00
		lc_ctrl_sec_cm	40.760s	911.851us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	35.890s	954.116us	50	50	100.00
		lc_ctrl_sec_cm	40.760s	911.851us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	35.890s	954.116us	50	50	100.00
		lc_ctrl_sec_cm	40.760s	911.851us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	13.670s	2.654ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.620s	88.241us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	25.570s	1.409ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	20.020s	3.195ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	20.020s	3.195ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	21.300s	6.249ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	14.890s	1.988ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	14.890s	1.988ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	2.964m	27.002ms	20	50	40.00
V3		TOTAL			20	50	40.00
		TOTAL			1000	1030	97.09

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.96	97.92	96.12	93.40	97.62	98.52	99.00	96.11

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 27 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 27 failures.
  - 1.lc_ctrl_stress_all_with_rand_reset.61402358148525278258066650620652108604852376200653916033696513119116943062647
    Line 145, in log /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2260284884 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2260284884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.lc_ctrl_stress_all_with_rand_reset.42449295148936103580316047146384791729994860253750569310944165393702256197242
    Line 7724, in log /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1432257842 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1432257842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 25 more failures.
UVM_ERROR (cip_base_vseq.sv:556) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 2 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 2 failures.
  - 3.lc_ctrl_stress_all_with_rand_reset.19000014530965250912349179387475543713898330406020182129918670838384351785467
    Line 15562, in log /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7080852967 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
  UVM_INFO @ 7080852967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 41.lc_ctrl_stress_all_with_rand_reset.13414824964663692286766730546385884140637063433662615656110177803686705740671
    Line 9224, in log /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 39413965271 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
  UVM_INFO @ 39413965271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (lc_ctrl_scoreboard.sv:241) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_cpu_en_o == exp_o.lc_cpu_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStProdEnd has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 25.lc_ctrl_stress_all_with_rand_reset.8740233582746031387129269915793761094808950859654157351616368246895097326479
    Line 4148, in log /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3664095099 ps: (lc_ctrl_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_cpu_en_o == exp_o.lc_cpu_en_o (5 [0x5] vs 10 [0xa]) Called from line: 100, LC_St DecLcStProdEnd
  UVM_INFO @ 3664095099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Thursday August 22 2024 22:02:20 UTC

GitHub Revision: 0825c81be0

Branch: os_regression_2024_08_22

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 102736032995262985039236458937944411119924968439319752111682827040046827694889

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `0825c81be0`