LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Saturday August 24 2024 20:40:24 UTC

GitHub Revision: 0825c81be0

Branch: os_regression_2024_08_24

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 60963866243502578220303968383308039937610555890224805106143103501951780280622

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	10.310s	155.240us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.660s	56.058us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.580s	16.735us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.710s	373.715us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.680s	25.661us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.640s	46.303us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.580s	16.735us	20	20	100.00
		lc_ctrl_csr_aliasing	1.680s	25.661us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	17.250s	534.491us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	28.440s	352.651us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.450s	12.973us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	7.750s	148.823us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	49.960s	294.011us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	25.500s	749.274us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	49.960s	294.011us	50	50	100.00
		lc_ctrl_prog_failure	7.750s	148.823us	50	50	100.00
		lc_ctrl_errors	25.500s	749.274us	50	50	100.00
		lc_ctrl_security_escalation	26.060s	2.248ms	50	50	100.00
		lc_ctrl_jtag_state_failure	2.321m	6.448ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	33.820s	1.096ms	20	20	100.00
		lc_ctrl_jtag_errors	2.484m	18.594ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	22.500s	7.480ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	32.080s	2.822ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	33.820s	1.096ms	20	20	100.00
		lc_ctrl_jtag_errors	2.484m	18.594ms	20	20	100.00
		lc_ctrl_jtag_access	36.080s	1.352ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	48.220s	5.906ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	6.020s	164.985us	10	10	100.00
		lc_ctrl_jtag_csr_rw	4.770s	1.861ms	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	29.560s	1.244ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	14.820s	514.638us	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.790s	188.142us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	6.730s	1.042ms	10	10	100.00
		lc_ctrl_jtag_alert_test	2.800s	463.972us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	31.380s	13.045ms	9	10	90.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.610s	30.064us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	6.000m	46.478ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.920s	27.796us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	7.880s	135.396us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	7.880s	135.396us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.660s	56.058us	5	5	100.00
		lc_ctrl_csr_rw	1.580s	16.735us	20	20	100.00
		lc_ctrl_csr_aliasing	1.680s	25.661us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.970s	28.766us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.660s	56.058us	5	5	100.00
		lc_ctrl_csr_rw	1.580s	16.735us	20	20	100.00
		lc_ctrl_csr_aliasing	1.680s	25.661us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.970s	28.766us	20	20	100.00
V2		TOTAL			698	700	99.71
V2S	tl_intg_err	lc_ctrl_sec_cm	56.130s	410.529us	5	5	100.00
		lc_ctrl_tl_intg_err	5.760s	127.130us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	5.760s	127.130us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	28.440s	352.651us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	49.960s	294.011us	50	50	100.00
		lc_ctrl_sec_cm	56.130s	410.529us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	49.960s	294.011us	50	50	100.00
		lc_ctrl_sec_cm	56.130s	410.529us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	49.960s	294.011us	50	50	100.00
		lc_ctrl_sec_cm	56.130s	410.529us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	49.960s	294.011us	50	50	100.00
		lc_ctrl_sec_cm	56.130s	410.529us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	49.960s	294.011us	50	50	100.00
		lc_ctrl_sec_cm	56.130s	410.529us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	49.960s	294.011us	50	50	100.00
		lc_ctrl_sec_cm	56.130s	410.529us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	49.960s	294.011us	50	50	100.00
		lc_ctrl_sec_cm	56.130s	410.529us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	49.960s	294.011us	50	50	100.00
		lc_ctrl_sec_cm	56.130s	410.529us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	26.060s	2.248ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	17.250s	534.491us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	32.080s	2.822ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	29.360s	764.405us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	29.360s	764.405us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	38.330s	2.150ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	24.730s	1.646ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	24.730s	1.646ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	3.693m	25.674ms	21	50	42.00
V3		TOTAL			21	50	42.00
		TOTAL			999	1030	96.99

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	25	92.59
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.00	97.92	95.84	93.40	97.62	98.52	99.25	96.47

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:867) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 25 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 25 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.94756951812325513924155826921249538300633106153129752755970056994895367625807
      Line 139, in log /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 112683321 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 112683321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.lc_ctrl_stress_all_with_rand_reset.5767391759908325694210756901522235727581209422374936465998674952191612696370
      Line 10500, in log /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3356989621 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3356989621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 23 more failures.

• UVM_ERROR (cip_base_vseq.sv:556) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 3 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 11.lc_ctrl_stress_all_with_rand_reset.4551561298301674670287073579990507241748769723447219126291155457655962585883
      Line 4412, in log /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 18308261370 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 18308261370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 17.lc_ctrl_stress_all_with_rand_reset.107463164051437063205329422803687670108512167230877572493130073342068263295523
      Line 3921, in log /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6501310157 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 6501310157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_FATAL (lc_ctrl_jtag_priority_vseq.sv:113) [lc_ctrl_jtag_priority_vseq] timeout occurred! has 1 failures:

  • Test lc_ctrl_jtag_priority has 1 failures.

    • 0.lc_ctrl_jtag_priority.45927606918759509496399677362506754812053164549171478579324723540095962786207
      Line 354, in log /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_priority/latest/run.log

        UVM_FATAL @ 10014054269 ps: (lc_ctrl_jtag_priority_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.lc_ctrl_jtag_priority_vseq] timeout occurred!
        UVM_INFO @ 10014054269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:304) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:

  • Test lc_ctrl_stress_all has 1 failures.

    • 30.lc_ctrl_stress_all.89648560456674390122407928689178040194580851393590819133459820058397929362587
      Line 3132, in log /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 3539537759 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 3539537759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_scoreboard.sv:243) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestLocked* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 38.lc_ctrl_stress_all_with_rand_reset.90689652366101708275065081383989737406136370560586943849504944969734199384670
      Line 338, in log /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  70887831 ps: (lc_ctrl_scoreboard.sv:243) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (10 [0xa] vs 5 [0x5]) Called from line: 100, LC_St DecLcStTestLocked1
        UVM_INFO @  70887831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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