LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Saturday August 24 2024 20:58:08 UTC

GitHub Revision: e733a8ef8a

Branch: os_regression_2024_08_24

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 36240513409906943553650221581975102764006655953510936167454320581301243659163

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	14.850s	2.824ms	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.720s	18.084us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.750s	15.134us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	3.310s	91.550us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	2.790s	162.911us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.550s	33.278us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.750s	15.134us	20	20	100.00
		lc_ctrl_csr_aliasing	2.790s	162.911us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	20.100s	313.599us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	34.120s	468.281us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.460s	19.831us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	8.960s	159.412us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	1.327m	1.688ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	31.850s	1.660ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	1.327m	1.688ms	50	50	100.00
		lc_ctrl_prog_failure	8.960s	159.412us	50	50	100.00
		lc_ctrl_errors	31.850s	1.660ms	50	50	100.00
		lc_ctrl_security_escalation	28.570s	1.240ms	50	50	100.00
		lc_ctrl_jtag_state_failure	3.062m	8.275ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	32.380s	12.667ms	20	20	100.00
		lc_ctrl_jtag_errors	2.660m	15.305ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	29.040s	3.032ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	37.890s	591.586us	20	20	100.00
		lc_ctrl_jtag_prog_failure	32.380s	12.667ms	20	20	100.00
		lc_ctrl_jtag_errors	2.660m	15.305ms	20	20	100.00
		lc_ctrl_jtag_access	40.930s	4.692ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	59.470s	1.352ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	7.640s	2.191ms	10	10	100.00
		lc_ctrl_jtag_csr_rw	6.160s	300.762us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	40.680s	6.916ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	46.080s	7.251ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.720s	148.100us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	5.910s	478.635us	10	10	100.00
		lc_ctrl_jtag_alert_test	3.530s	377.344us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	47.500s	5.258ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.710s	14.034us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	12.750m	74.232ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	2.260s	43.408us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	8.910s	609.221us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	8.910s	609.221us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.720s	18.084us	5	5	100.00
		lc_ctrl_csr_rw	1.750s	15.134us	20	20	100.00
		lc_ctrl_csr_aliasing	2.790s	162.911us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.810s	185.965us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.720s	18.084us	5	5	100.00
		lc_ctrl_csr_rw	1.750s	15.134us	20	20	100.00
		lc_ctrl_csr_aliasing	2.790s	162.911us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.810s	185.965us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	1.454m	418.453us	5	5	100.00
		lc_ctrl_tl_intg_err	6.130s	118.314us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	6.130s	118.314us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	34.120s	468.281us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	1.327m	1.688ms	50	50	100.00
		lc_ctrl_sec_cm	1.454m	418.453us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	1.327m	1.688ms	50	50	100.00
		lc_ctrl_sec_cm	1.454m	418.453us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	1.327m	1.688ms	50	50	100.00
		lc_ctrl_sec_cm	1.454m	418.453us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	1.327m	1.688ms	50	50	100.00
		lc_ctrl_sec_cm	1.454m	418.453us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	1.327m	1.688ms	50	50	100.00
		lc_ctrl_sec_cm	1.454m	418.453us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	1.327m	1.688ms	50	50	100.00
		lc_ctrl_sec_cm	1.454m	418.453us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	1.327m	1.688ms	50	50	100.00
		lc_ctrl_sec_cm	1.454m	418.453us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	1.327m	1.688ms	50	50	100.00
		lc_ctrl_sec_cm	1.454m	418.453us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	28.570s	1.240ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	20.100s	313.599us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	37.890s	591.586us	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	40.800s	2.376ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	40.800s	2.376ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	31.990s	5.627ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	26.940s	3.044ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	26.940s	3.044ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	4.288m	6.457ms	24	50	48.00
V3		TOTAL			24	50	48.00
		TOTAL			1004	1030	97.48

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.27	97.92	95.93	93.40	100.00	98.52	99.00	96.11

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:867) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 22 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 22 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.12386169386157130734065740215630603062358163432342539825240984673251703499
      Line 213, in log /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 900930618 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 900930618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.lc_ctrl_stress_all_with_rand_reset.20650347847641205503129110650725402453902940438988170969740450406017234850722
      Line 908, in log /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4358304078 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 4358304078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 20 more failures.

• UVM_ERROR (cip_base_vseq.sv:556) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 4 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 4 failures.

    • 6.lc_ctrl_stress_all_with_rand_reset.24826185945377593138434595850092598879086121981728799018257663465085317143383
      Line 2599, in log /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1774168502 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 1774168502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 20.lc_ctrl_stress_all_with_rand_reset.27632384389141318279888635530768855309485607252625245511852424004404687529719
      Line 12063, in log /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6456595749 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 6456595749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 2 more failures.

Past Results

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