LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Monday August 26 2024 23:33:20 UTC

GitHub Revision: `4674f625b3`

Branch: os_regression_2024_08_26

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 27137705585251537962012108482438895412147493342955425380690984800523869492310

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	6.760s	87.115us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.390s	36.929us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.410s	12.231us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.090s	164.577us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.620s	80.072us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.330s	99.364us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.410s	12.231us	20	20	100.00
		lc_ctrl_csr_aliasing	1.620s	80.072us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	15.710s	192.419us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	22.370s	1.869ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.270s	20.433us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.400s	117.055us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	35.940s	2.931ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	22.830s	1.651ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	35.940s	2.931ms	50	50	100.00
		lc_ctrl_prog_failure	5.400s	117.055us	50	50	100.00
		lc_ctrl_errors	22.830s	1.651ms	50	50	100.00
		lc_ctrl_security_escalation	17.750s	1.161ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.588m	11.901ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	21.630s	5.246ms	20	20	100.00
		lc_ctrl_jtag_errors	1.256m	5.420ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	14.350s	421.219us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	31.530s	3.372ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	21.630s	5.246ms	20	20	100.00
		lc_ctrl_jtag_errors	1.256m	5.420ms	20	20	100.00
		lc_ctrl_jtag_access	25.900s	4.914ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	39.820s	3.135ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	4.690s	1.023ms	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.270s	89.861us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	31.890s	20.199ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	23.580s	4.760ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.080s	93.396us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	5.710s	2.702ms	10	10	100.00
		lc_ctrl_jtag_alert_test	2.400s	457.344us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	26.190s	4.375ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.660s	26.122us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	18.884m	75.432ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.920s	37.266us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.920s	122.680us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.920s	122.680us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.390s	36.929us	5	5	100.00
		lc_ctrl_csr_rw	1.410s	12.231us	20	20	100.00
		lc_ctrl_csr_aliasing	1.620s	80.072us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.760s	52.312us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.390s	36.929us	5	5	100.00
		lc_ctrl_csr_rw	1.410s	12.231us	20	20	100.00
		lc_ctrl_csr_aliasing	1.620s	80.072us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.760s	52.312us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	36.760s	413.932us	5	5	100.00
		lc_ctrl_tl_intg_err	4.130s	219.290us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.130s	219.290us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	22.370s	1.869ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	35.940s	2.931ms	50	50	100.00
		lc_ctrl_sec_cm	36.760s	413.932us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	35.940s	2.931ms	50	50	100.00
		lc_ctrl_sec_cm	36.760s	413.932us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	35.940s	2.931ms	50	50	100.00
		lc_ctrl_sec_cm	36.760s	413.932us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	35.940s	2.931ms	50	50	100.00
		lc_ctrl_sec_cm	36.760s	413.932us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	35.940s	2.931ms	50	50	100.00
		lc_ctrl_sec_cm	36.760s	413.932us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	35.940s	2.931ms	50	50	100.00
		lc_ctrl_sec_cm	36.760s	413.932us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	35.940s	2.931ms	50	50	100.00
		lc_ctrl_sec_cm	36.760s	413.932us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	35.940s	2.931ms	50	50	100.00
		lc_ctrl_sec_cm	36.760s	413.932us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	17.750s	1.161ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	15.710s	192.419us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	31.530s	3.372ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	26.490s	1.508ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	26.490s	1.508ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	24.800s	1.175ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	19.360s	3.061ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	19.360s	3.061ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	2.820m	4.067ms	24	50	48.00
V3		TOTAL			24	50	48.00
		TOTAL			1004	1030	97.48

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.99	97.92	95.84	93.40	97.62	98.52	99.00	96.64

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 25 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 25 failures.
  - 0.lc_ctrl_stress_all_with_rand_reset.9326747717995718113928012891079576553223333555475920602641932881002834136205
    Line 141, in log /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 829629745 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 829629745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.lc_ctrl_stress_all_with_rand_reset.53101031826571210723151702121045009243369579097504169118207871219033468821784
    Line 343, in log /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1021530720 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1021530720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 23 more failures.
UVM_ERROR (lc_ctrl_scoreboard.sv:238) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestUnlocked* has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 40.lc_ctrl_stress_all_with_rand_reset.35575999277119534010303933697811650134332631724360320053121415606722403560143
    Line 3361, in log /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2767125104 ps: (lc_ctrl_scoreboard.sv:238) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (5 [0x5] vs 10 [0xa]) Called from line: 100, LC_St DecLcStTestUnlocked6
  UVM_INFO @ 2767125104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Monday August 26 2024 23:33:20 UTC

GitHub Revision: 4674f625b3

Branch: os_regression_2024_08_26

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 27137705585251537962012108482438895412147493342955425380690984800523869492310

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `4674f625b3`