LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Wednesday August 28 2024 16:26:26 UTC

GitHub Revision: a861deb3de

Branch: os_regression_2024_08_28

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1071354200461384473511155521960728188378582408849032283874664554749864050652

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	12.920s	141.532us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.540s	25.218us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.540s	13.316us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	4.740s	757.677us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	2.120s	63.880us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.660s	31.579us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.540s	13.316us	20	20	100.00
		lc_ctrl_csr_aliasing	2.120s	63.880us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	15.890s	566.197us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	31.120s	2.852ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.430s	22.837us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	6.500s	192.400us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	40.710s	776.609us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	30.420s	706.083us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	40.710s	776.609us	50	50	100.00
		lc_ctrl_prog_failure	6.500s	192.400us	50	50	100.00
		lc_ctrl_errors	30.420s	706.083us	50	50	100.00
		lc_ctrl_security_escalation	21.070s	524.461us	50	50	100.00
		lc_ctrl_jtag_state_failure	2.179m	13.363ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	24.740s	813.710us	20	20	100.00
		lc_ctrl_jtag_errors	1.698m	6.211ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	18.310s	605.950us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	47.770s	8.661ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	24.740s	813.710us	20	20	100.00
		lc_ctrl_jtag_errors	1.698m	6.211ms	20	20	100.00
		lc_ctrl_jtag_access	26.780s	882.972us	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	35.570s	1.300ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	5.380s	190.980us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.530s	581.682us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	30.060s	2.214ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	16.670s	4.489ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.170s	21.145us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	7.450s	3.148ms	10	10	100.00
		lc_ctrl_jtag_alert_test	2.260s	33.195us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	28.290s	844.187us	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.630s	69.387us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	10.814m	49.453ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	2.030s	187.933us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	7.260s	497.361us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	7.260s	497.361us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.540s	25.218us	5	5	100.00
		lc_ctrl_csr_rw	1.540s	13.316us	20	20	100.00
		lc_ctrl_csr_aliasing	2.120s	63.880us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.290s	36.868us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.540s	25.218us	5	5	100.00
		lc_ctrl_csr_rw	1.540s	13.316us	20	20	100.00
		lc_ctrl_csr_aliasing	2.120s	63.880us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.290s	36.868us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	46.000s	1.056ms	5	5	100.00
		lc_ctrl_tl_intg_err	6.880s	468.176us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	6.880s	468.176us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	31.120s	2.852ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	40.710s	776.609us	50	50	100.00
		lc_ctrl_sec_cm	46.000s	1.056ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	40.710s	776.609us	50	50	100.00
		lc_ctrl_sec_cm	46.000s	1.056ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	40.710s	776.609us	50	50	100.00
		lc_ctrl_sec_cm	46.000s	1.056ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	40.710s	776.609us	50	50	100.00
		lc_ctrl_sec_cm	46.000s	1.056ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	40.710s	776.609us	50	50	100.00
		lc_ctrl_sec_cm	46.000s	1.056ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	40.710s	776.609us	50	50	100.00
		lc_ctrl_sec_cm	46.000s	1.056ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	40.710s	776.609us	50	50	100.00
		lc_ctrl_sec_cm	46.000s	1.056ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	40.710s	776.609us	50	50	100.00
		lc_ctrl_sec_cm	46.000s	1.056ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	21.070s	524.461us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	15.890s	566.197us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	47.770s	8.661ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	38.740s	1.513ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	38.740s	1.513ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	29.490s	18.582ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	21.190s	652.549us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	21.190s	652.549us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	2.987m	22.934ms	18	50	36.00
V3		TOTAL			18	50	36.00
		TOTAL			997	1030	96.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.27	97.92	95.84	93.40	100.00	98.52	98.76	96.47

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:867) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 25 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 25 failures.

    • 3.lc_ctrl_stress_all_with_rand_reset.79300889401623936110720347198748191835417642032886204562955037019657170807480
      Line 5991, in log /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 8409095987 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 8409095987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.lc_ctrl_stress_all_with_rand_reset.67914128982793258841971837834351466694284237390860410818682505569150510663329
      Line 862, in log /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7153757086 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 7153757086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 23 more failures.

• UVM_ERROR (cip_base_vseq.sv:556) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 3 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 5.lc_ctrl_stress_all_with_rand_reset.59640336013934066259399562364572805741110062216529530712150056952089759376062
      Line 5599, in log /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1804063080 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 1804063080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 31.lc_ctrl_stress_all_with_rand_reset.9976585389723262317913040365550102830431187283212673768542804123731520970313
      Line 3364, in log /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4783190963 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 4783190963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR (cip_base_vseq.sv:771) [lc_ctrl_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 18.lc_ctrl_stress_all_with_rand_reset.26780099981579076302498452016836527904121610980173510894096632839242266327297
      Line 3287, in log /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3105137448 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 3105137448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:304) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:

  • Test lc_ctrl_stress_all has 1 failures.

    • 22.lc_ctrl_stress_all.91798190428378875079841739546875458479904428421331117410061627070765517402841
      Line 11773, in log /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 32144002135 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 32144002135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_scoreboard.sv:243) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestLocked* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 28.lc_ctrl_stress_all_with_rand_reset.75035073694096808569409055007359727254764863727573777635480978231240294696535
      Line 4417, in log /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 345373761 ps: (lc_ctrl_scoreboard.sv:243) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (10 [0xa] vs 5 [0x5]) Called from line: 100, LC_St DecLcStTestLocked6
        UVM_INFO @ 345373761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job timed out after * minutes has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 34.lc_ctrl_stress_all_with_rand_reset.17527853046353550329839661351937393207441779936013281404732005910066501185397
      Log /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job timed out after 180 minutes
      

• UVM_ERROR (cip_base_vseq.sv:556) [lc_ctrl_smoke_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_prog_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 44.lc_ctrl_stress_all_with_rand_reset.87375384409380429196047782628847150837102757143714829122380367168638116903620
      Line 197, in log /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  46802007 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_smoke_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_prog_error fired unexpectedly!
        UVM_INFO @  46802007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.08.28_06.56.20
• 2024.08.26_02.17.41
• 2024.08.24_20.49.25
• 2024.08.24_20.06.49
• 2024.08.22_14.08.24
• 2024.08.20_07.52.13
• 2024.08.19_08.05.57