LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Sunday September 01 2024 02:56:32 UTC

GitHub Revision: `ed1c41cd0f`

Branch: os_regression_2024_08_31

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 79046303479535931055412478968949166876277637335647713094117953182855865639399

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	8.560s	212.337us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.650s	30.647us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.580s	14.620us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	3.150s	200.299us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	2.400s	205.597us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.290s	155.503us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.580s	14.620us	20	20	100.00
		lc_ctrl_csr_aliasing	2.400s	205.597us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	18.650s	60.754us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	21.190s	411.053us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.390s	11.288us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	8.230s	167.831us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	54.510s	1.406ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	26.650s	2.143ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	54.510s	1.406ms	50	50	100.00
		lc_ctrl_prog_failure	8.230s	167.831us	50	50	100.00
		lc_ctrl_errors	26.650s	2.143ms	50	50	100.00
		lc_ctrl_security_escalation	23.070s	847.307us	50	50	100.00
		lc_ctrl_jtag_state_failure	2.078m	13.132ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	30.040s	1.822ms	20	20	100.00
		lc_ctrl_jtag_errors	1.997m	15.042ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	24.890s	680.530us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	57.500s	8.953ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	30.040s	1.822ms	20	20	100.00
		lc_ctrl_jtag_errors	1.997m	15.042ms	20	20	100.00
		lc_ctrl_jtag_access	21.980s	791.315us	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	57.360s	10.475ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	9.610s	264.382us	10	10	100.00
		lc_ctrl_jtag_csr_rw	5.150s	242.758us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	34.230s	1.524ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	20.970s	1.027ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.130s	87.612us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	6.240s	134.961us	10	10	100.00
		lc_ctrl_jtag_alert_test	4.270s	100.856us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	1.229m	6.256ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.710s	14.150us	48	50	96.00
V2	stress_all	lc_ctrl_stress_all	9.875m	16.470ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	2.030s	146.548us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.490s	110.943us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.490s	110.943us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.650s	30.647us	5	5	100.00
		lc_ctrl_csr_rw	1.580s	14.620us	20	20	100.00
		lc_ctrl_csr_aliasing	2.400s	205.597us	5	5	100.00
		lc_ctrl_same_csr_outstanding	3.000s	192.697us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.650s	30.647us	5	5	100.00
		lc_ctrl_csr_rw	1.580s	14.620us	20	20	100.00
		lc_ctrl_csr_aliasing	2.400s	205.597us	5	5	100.00
		lc_ctrl_same_csr_outstanding	3.000s	192.697us	20	20	100.00
V2		TOTAL			698	700	99.71
V2S	tl_intg_err	lc_ctrl_sec_cm	57.780s	225.556us	5	5	100.00
		lc_ctrl_tl_intg_err	4.690s	337.707us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.690s	337.707us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	21.190s	411.053us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	54.510s	1.406ms	50	50	100.00
		lc_ctrl_sec_cm	57.780s	225.556us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	54.510s	1.406ms	50	50	100.00
		lc_ctrl_sec_cm	57.780s	225.556us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	54.510s	1.406ms	50	50	100.00
		lc_ctrl_sec_cm	57.780s	225.556us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	54.510s	1.406ms	50	50	100.00
		lc_ctrl_sec_cm	57.780s	225.556us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	54.510s	1.406ms	50	50	100.00
		lc_ctrl_sec_cm	57.780s	225.556us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	54.510s	1.406ms	50	50	100.00
		lc_ctrl_sec_cm	57.780s	225.556us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	54.510s	1.406ms	50	50	100.00
		lc_ctrl_sec_cm	57.780s	225.556us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	54.510s	1.406ms	50	50	100.00
		lc_ctrl_sec_cm	57.780s	225.556us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	23.070s	847.307us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	18.650s	60.754us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	57.500s	8.953ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	32.430s	785.116us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	32.430s	785.116us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	36.020s	4.513ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	24.360s	1.541ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	24.360s	1.541ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	4.341m	6.251ms	29	50	58.00
V3		TOTAL			29	50	58.00
		TOTAL			1007	1030	97.77

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.30	97.92	95.75	93.40	100.00	98.52	99.25	96.29

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 18 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 18 failures.
  - 3.lc_ctrl_stress_all_with_rand_reset.68546005058096729082681287670803570473889191786875915262051017345167337653932
    Line 9974, in log /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2573732005 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2573732005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.lc_ctrl_stress_all_with_rand_reset.10259514299275422534100144298552512852139461549911617713658532357632482413968
    Line 815, in log /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 509617475 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 509617475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 16 more failures.
UVM_ERROR (cip_base_vseq.sv:556) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 3 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 3 failures.
  - 13.lc_ctrl_stress_all_with_rand_reset.58215732482199806299267970025219854907745302017871251056830439070432650847961
    Line 9936, in log /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4752345036 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
  UVM_INFO @ 4752345036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 20.lc_ctrl_stress_all_with_rand_reset.76512188457322439161338831413827164408401216535535413157577194034165668203654
    Line 2097, in log /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 23810730406 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
  UVM_INFO @ 23810730406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout lc_ctrl_reg_block.status.token_error (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1) has 2 failures:
- Test lc_ctrl_volatile_unlock_smoke has 2 failures.
  - 6.lc_ctrl_volatile_unlock_smoke.57527581597713325010910701940991470688630095062268207030022938036047273549618
    Line 135, in log /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_volatile_unlock_smoke/latest/run.log
```
  UVM_FATAL @ 124248761 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout lc_ctrl_reg_block.status.token_error (addr=0x27400704, Comparison=CompareOpEq, exp_data=0x1, call_count=1)
  UVM_INFO @ 124248761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 45.lc_ctrl_volatile_unlock_smoke.55271437220593468125324183616551590445601947678950872535084411608469141286909
    Line 135, in log /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_volatile_unlock_smoke/latest/run.log
```
  UVM_FATAL @ 118359425 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout lc_ctrl_reg_block.status.token_error (addr=0x71752a04, Comparison=CompareOpEq, exp_data=0x1, call_count=1)
  UVM_INFO @ 118359425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Sunday September 01 2024 02:56:32 UTC

GitHub Revision: ed1c41cd0f

Branch: os_regression_2024_08_31

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 79046303479535931055412478968949166876277637335647713094117953182855865639399

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `ed1c41cd0f`