372a6306e0
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | lc_ctrl_smoke | 20.000s | 263.347us | 50 | 50 | 100.00 |
V1 | csr_hw_reset | lc_ctrl_csr_hw_reset | 1.650s | 18.641us | 5 | 5 | 100.00 |
V1 | csr_rw | lc_ctrl_csr_rw | 1.590s | 81.236us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | lc_ctrl_csr_bit_bash | 3.690s | 214.906us | 5 | 5 | 100.00 |
V1 | csr_aliasing | lc_ctrl_csr_aliasing | 1.770s | 33.242us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | lc_ctrl_csr_mem_rw_with_rand_reset | 3.030s | 108.015us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | lc_ctrl_csr_rw | 1.590s | 81.236us | 20 | 20 | 100.00 |
lc_ctrl_csr_aliasing | 1.770s | 33.242us | 5 | 5 | 100.00 | ||
V1 | TOTAL | 105 | 105 | 100.00 | |||
V2 | state_post_trans | lc_ctrl_state_post_trans | 12.120s | 254.294us | 50 | 50 | 100.00 |
V2 | regwen_during_op | lc_ctrl_regwen_during_op | 14.340s | 271.519us | 10 | 10 | 100.00 |
V2 | rand_wr_claim_transition_if | lc_ctrl_claim_transition_if | 1.380s | 39.101us | 10 | 10 | 100.00 |
V2 | lc_prog_failure | lc_ctrl_prog_failure | 5.960s | 659.203us | 50 | 50 | 100.00 |
V2 | lc_state_failure | lc_ctrl_state_failure | 40.500s | 2.502ms | 50 | 50 | 100.00 |
V2 | lc_errors | lc_ctrl_errors | 25.820s | 469.524us | 50 | 50 | 100.00 |
V2 | security_escalation | lc_ctrl_state_failure | 40.500s | 2.502ms | 50 | 50 | 100.00 |
lc_ctrl_prog_failure | 5.960s | 659.203us | 50 | 50 | 100.00 | ||
lc_ctrl_errors | 25.820s | 469.524us | 50 | 50 | 100.00 | ||
lc_ctrl_security_escalation | 19.770s | 2.582ms | 50 | 50 | 100.00 | ||
lc_ctrl_jtag_state_failure | 1.876m | 6.840ms | 20 | 20 | 100.00 | ||
lc_ctrl_jtag_prog_failure | 17.300s | 586.256us | 20 | 20 | 100.00 | ||
lc_ctrl_jtag_errors | 2.048m | 4.639ms | 20 | 20 | 100.00 | ||
V2 | jtag_access | lc_ctrl_jtag_smoke | 11.720s | 666.776us | 20 | 20 | 100.00 |
lc_ctrl_jtag_state_post_trans | 38.010s | 4.256ms | 20 | 20 | 100.00 | ||
lc_ctrl_jtag_prog_failure | 17.300s | 586.256us | 20 | 20 | 100.00 | ||
lc_ctrl_jtag_errors | 2.048m | 4.639ms | 20 | 20 | 100.00 | ||
lc_ctrl_jtag_access | 19.750s | 640.678us | 50 | 50 | 100.00 | ||
lc_ctrl_jtag_regwen_during_op | 43.790s | 5.387ms | 10 | 10 | 100.00 | ||
lc_ctrl_jtag_csr_hw_reset | 7.020s | 187.602us | 10 | 10 | 100.00 | ||
lc_ctrl_jtag_csr_rw | 3.500s | 68.757us | 10 | 10 | 100.00 | ||
lc_ctrl_jtag_csr_bit_bash | 22.800s | 4.566ms | 10 | 10 | 100.00 | ||
lc_ctrl_jtag_csr_aliasing | 21.460s | 4.145ms | 10 | 10 | 100.00 | ||
lc_ctrl_jtag_same_csr_outstanding | 2.580s | 791.831us | 10 | 10 | 100.00 | ||
lc_ctrl_jtag_csr_mem_rw_with_rand_reset | 8.400s | 5.839ms | 10 | 10 | 100.00 | ||
lc_ctrl_jtag_alert_test | 3.280s | 66.609us | 10 | 10 | 100.00 | ||
V2 | jtag_priority | lc_ctrl_jtag_priority | 40.090s | 1.664ms | 10 | 10 | 100.00 |
V2 | lc_ctrl_volatile_unlock | lc_ctrl_volatile_unlock_smoke | 1.830s | 61.396us | 50 | 50 | 100.00 |
V2 | stress_all | lc_ctrl_stress_all | 16.573m | 131.966ms | 50 | 50 | 100.00 |
V2 | alert_test | lc_ctrl_alert_test | 2.350s | 39.462us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | lc_ctrl_tl_errors | 7.700s | 170.522us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | lc_ctrl_tl_errors | 7.700s | 170.522us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | lc_ctrl_csr_hw_reset | 1.650s | 18.641us | 5 | 5 | 100.00 |
lc_ctrl_csr_rw | 1.590s | 81.236us | 20 | 20 | 100.00 | ||
lc_ctrl_csr_aliasing | 1.770s | 33.242us | 5 | 5 | 100.00 | ||
lc_ctrl_same_csr_outstanding | 2.110s | 295.549us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | lc_ctrl_csr_hw_reset | 1.650s | 18.641us | 5 | 5 | 100.00 |
lc_ctrl_csr_rw | 1.590s | 81.236us | 20 | 20 | 100.00 | ||
lc_ctrl_csr_aliasing | 1.770s | 33.242us | 5 | 5 | 100.00 | ||
lc_ctrl_same_csr_outstanding | 2.110s | 295.549us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 700 | 700 | 100.00 | |||
V2S | tl_intg_err | lc_ctrl_sec_cm | 35.720s | 223.344us | 5 | 5 | 100.00 |
lc_ctrl_tl_intg_err | 5.310s | 468.465us | 20 | 20 | 100.00 | ||
V2S | sec_cm_bus_integrity | lc_ctrl_tl_intg_err | 5.310s | 468.465us | 20 | 20 | 100.00 |
V2S | sec_cm_transition_config_regwen | lc_ctrl_regwen_during_op | 14.340s | 271.519us | 10 | 10 | 100.00 |
V2S | sec_cm_manuf_state_sparse | lc_ctrl_state_failure | 40.500s | 2.502ms | 50 | 50 | 100.00 |
lc_ctrl_sec_cm | 35.720s | 223.344us | 5 | 5 | 100.00 | ||
V2S | sec_cm_transition_ctr_sparse | lc_ctrl_state_failure | 40.500s | 2.502ms | 50 | 50 | 100.00 |
lc_ctrl_sec_cm | 35.720s | 223.344us | 5 | 5 | 100.00 | ||
V2S | sec_cm_manuf_state_bkgn_chk | lc_ctrl_state_failure | 40.500s | 2.502ms | 50 | 50 | 100.00 |
lc_ctrl_sec_cm | 35.720s | 223.344us | 5 | 5 | 100.00 | ||
V2S | sec_cm_transition_ctr_bkgn_chk | lc_ctrl_state_failure | 40.500s | 2.502ms | 50 | 50 | 100.00 |
lc_ctrl_sec_cm | 35.720s | 223.344us | 5 | 5 | 100.00 | ||
V2S | sec_cm_state_config_sparse | lc_ctrl_state_failure | 40.500s | 2.502ms | 50 | 50 | 100.00 |
lc_ctrl_sec_cm | 35.720s | 223.344us | 5 | 5 | 100.00 | ||
V2S | sec_cm_main_fsm_sparse | lc_ctrl_state_failure | 40.500s | 2.502ms | 50 | 50 | 100.00 |
lc_ctrl_sec_cm | 35.720s | 223.344us | 5 | 5 | 100.00 | ||
V2S | sec_cm_kmac_fsm_sparse | lc_ctrl_state_failure | 40.500s | 2.502ms | 50 | 50 | 100.00 |
lc_ctrl_sec_cm | 35.720s | 223.344us | 5 | 5 | 100.00 | ||
V2S | sec_cm_main_fsm_local_esc | lc_ctrl_state_failure | 40.500s | 2.502ms | 50 | 50 | 100.00 |
lc_ctrl_sec_cm | 35.720s | 223.344us | 5 | 5 | 100.00 | ||
V2S | sec_cm_main_fsm_global_esc | lc_ctrl_security_escalation | 19.770s | 2.582ms | 50 | 50 | 100.00 |
V2S | sec_cm_main_ctrl_flow_consistency | lc_ctrl_state_post_trans | 12.120s | 254.294us | 50 | 50 | 100.00 |
lc_ctrl_jtag_state_post_trans | 38.010s | 4.256ms | 20 | 20 | 100.00 | ||
V2S | sec_cm_intersig_mubi | lc_ctrl_sec_mubi | 27.210s | 779.492us | 50 | 50 | 100.00 |
V2S | sec_cm_token_valid_ctrl_mubi | lc_ctrl_sec_mubi | 27.210s | 779.492us | 50 | 50 | 100.00 |
V2S | sec_cm_token_digest | lc_ctrl_sec_token_digest | 28.170s | 8.427ms | 50 | 50 | 100.00 |
V2S | sec_cm_token_mux_ctrl_redun | lc_ctrl_sec_token_mux | 28.510s | 1.696ms | 50 | 50 | 100.00 |
V2S | sec_cm_token_valid_mux_redun | lc_ctrl_sec_token_mux | 28.510s | 1.696ms | 50 | 50 | 100.00 |
V2S | TOTAL | 175 | 175 | 100.00 | |||
V3 | stress_all_with_rand_reset | lc_ctrl_stress_all_with_rand_reset | 2.693m | 4.652ms | 21 | 50 | 42.00 |
V3 | TOTAL | 21 | 50 | 42.00 | |||
TOTAL | 1001 | 1030 | 97.18 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 6 | 6 | 6 | 100.00 |
V2 | 27 | 27 | 27 | 100.00 |
V2S | 5 | 5 | 5 | 100.00 |
V3 | 1 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
97.23 | 97.92 | 95.93 | 93.40 | 100.00 | 98.52 | 98.76 | 96.11 |
UVM_ERROR (cip_base_vseq.sv:867) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
has 24 failures:
0.lc_ctrl_stress_all_with_rand_reset.57782842828194855726673739882307538224782845304326795539531844581076184332824
Line 234, in log /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 461633122 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 461633122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.lc_ctrl_stress_all_with_rand_reset.17899346841030824406265839627054741966500432683430184883187906248901423027623
Line 5212, in log /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1047650386 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1047650386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 22 more failures.
UVM_ERROR (cip_base_vseq.sv:556) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly!
has 4 failures:
20.lc_ctrl_stress_all_with_rand_reset.84160763515353281718292183642559666596492040687226763545757157456724175394164
Line 2710, in log /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2832363452 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
UVM_INFO @ 2832363452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
28.lc_ctrl_stress_all_with_rand_reset.62753186209890128700013707665444948617527549680564387535017961528761907363017
Line 2573, in log /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4136177254 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
UVM_INFO @ 4136177254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (cip_base_vseq.sv:556) [lc_ctrl_smoke_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_prog_error fired unexpectedly!
has 1 failures:
31.lc_ctrl_stress_all_with_rand_reset.39824621096963699456155165152197268625545704167982543363447105300258501253675
Line 674, in log /workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 376034058 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_smoke_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_prog_error fired unexpectedly!
UVM_INFO @ 376034058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---