LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Monday September 09 2024 02:20:26 UTC

GitHub Revision: `af2d1709f9`

Branch: os_regression_2024_09_08

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 13980492992314588037778262839223440914483141513139750793389284041724730149540

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	9.250s	125.056us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.790s	17.849us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.570s	16.993us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.820s	82.658us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	2.080s	36.059us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.150s	41.926us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.570s	16.993us	20	20	100.00
		lc_ctrl_csr_aliasing	2.080s	36.059us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	13.580s	180.200us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	25.340s	1.782ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.500s	11.109us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.730s	168.423us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	41.420s	1.232ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	23.550s	2.100ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	41.420s	1.232ms	50	50	100.00
		lc_ctrl_prog_failure	5.730s	168.423us	50	50	100.00
		lc_ctrl_errors	23.550s	2.100ms	50	50	100.00
		lc_ctrl_security_escalation	19.060s	914.531us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.895m	4.024ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	14.910s	2.066ms	20	20	100.00
		lc_ctrl_jtag_errors	1.635m	3.794ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	12.880s	1.355ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	28.740s	18.303ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	14.910s	2.066ms	20	20	100.00
		lc_ctrl_jtag_errors	1.635m	3.794ms	20	20	100.00
		lc_ctrl_jtag_access	24.170s	1.894ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	35.130s	4.789ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.740s	122.701us	10	10	100.00
		lc_ctrl_jtag_csr_rw	4.200s	175.679us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	23.190s	2.329ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	25.370s	9.256ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.470s	40.404us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	6.600s	262.751us	10	10	100.00
		lc_ctrl_jtag_alert_test	1.870s	44.102us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	24.030s	12.386ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.660s	14.495us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	12.720m	29.340ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	2.030s	60.024us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.540s	1.341ms	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.540s	1.341ms	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.790s	17.849us	5	5	100.00
		lc_ctrl_csr_rw	1.570s	16.993us	20	20	100.00
		lc_ctrl_csr_aliasing	2.080s	36.059us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.420s	49.786us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.790s	17.849us	5	5	100.00
		lc_ctrl_csr_rw	1.570s	16.993us	20	20	100.00
		lc_ctrl_csr_aliasing	2.080s	36.059us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.420s	49.786us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	44.440s	980.843us	5	5	100.00
		lc_ctrl_tl_intg_err	4.570s	1.246ms	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.570s	1.246ms	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	25.340s	1.782ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	41.420s	1.232ms	50	50	100.00
		lc_ctrl_sec_cm	44.440s	980.843us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	41.420s	1.232ms	50	50	100.00
		lc_ctrl_sec_cm	44.440s	980.843us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	41.420s	1.232ms	50	50	100.00
		lc_ctrl_sec_cm	44.440s	980.843us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	41.420s	1.232ms	50	50	100.00
		lc_ctrl_sec_cm	44.440s	980.843us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	41.420s	1.232ms	50	50	100.00
		lc_ctrl_sec_cm	44.440s	980.843us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	41.420s	1.232ms	50	50	100.00
		lc_ctrl_sec_cm	44.440s	980.843us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	41.420s	1.232ms	50	50	100.00
		lc_ctrl_sec_cm	44.440s	980.843us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	41.420s	1.232ms	50	50	100.00
		lc_ctrl_sec_cm	44.440s	980.843us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	19.060s	914.531us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	13.580s	180.200us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	28.740s	18.303ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	24.970s	1.421ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	24.970s	1.421ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	25.670s	752.142us	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	22.930s	555.632us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	22.930s	555.632us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	2.812m	3.727ms	33	50	66.00
V3		TOTAL			33	50	66.00
		TOTAL			1012	1030	98.25

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.25	97.92	95.84	93.40	100.00	98.52	98.76	96.29

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 15 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 15 failures.
  - 4.lc_ctrl_stress_all_with_rand_reset.64810122137556513136844514837182689494385448474785805078608420723194636455932
    Line 384, in log /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4680604845 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4680604845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.lc_ctrl_stress_all_with_rand_reset.56894703058617637404275612274352876747525659787011746733411935622928629562138
    Line 6681, in log /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8257728552 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 8257728552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 13 more failures.
UVM_ERROR (cip_base_vseq.sv:556) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 2 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 2 failures.
  - 36.lc_ctrl_stress_all_with_rand_reset.86912073431480970775699550537075544396049122881316682778129054367610937678784
    Line 11778, in log /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 20068560823 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
  UVM_INFO @ 20068560823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 47.lc_ctrl_stress_all_with_rand_reset.968372597015930112223800723261460966995787744075003794076863300760580932896
    Line 2930, in log /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9142846911 ps: (cip_base_vseq.sv:556) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
  UVM_INFO @ 9142846911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:304) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:
- Test lc_ctrl_stress_all has 1 failures.
  - 46.lc_ctrl_stress_all.55208230040323568050313168186273836107716474470550058731199897957296181722076
    Line 4068, in log /workspaces/repo/scratch/os_regression_2024_09_08/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_stress_all/latest/run.log
```
  UVM_ERROR @ 8959481328 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
  UVM_INFO @ 8959481328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Monday September 09 2024 02:20:26 UTC

GitHub Revision: af2d1709f9

Branch: os_regression_2024_09_08

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 13980492992314588037778262839223440914483141513139750793389284041724730149540

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `af2d1709f9`