LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Tuesday May 07 2024 19:02:25 UTC

GitHub Revision: 18c8953cf1

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 23463731882259624708557902606691160899163550314542713462365308032920382521803

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	7.150s	254.912us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.130s	18.108us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.120s	112.852us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.690s	74.253us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.730s	37.498us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.790s	39.007us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.120s	112.852us	20	20	100.00
		lc_ctrl_csr_aliasing	1.730s	37.498us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	9.600s	97.862us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	26.860s	418.243us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.980s	13.370us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.660s	206.385us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	38.110s	359.963us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	24.780s	4.118ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	38.110s	359.963us	50	50	100.00
		lc_ctrl_prog_failure	4.660s	206.385us	50	50	100.00
		lc_ctrl_errors	24.780s	4.118ms	50	50	100.00
		lc_ctrl_security_escalation	15.490s	1.519ms	50	50	100.00
		lc_ctrl_jtag_state_failure	2.148m	17.923ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	25.570s	4.166ms	20	20	100.00
		lc_ctrl_jtag_errors	1.388m	3.135ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	16.270s	576.410us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	37.640s	1.408ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	25.570s	4.166ms	20	20	100.00
		lc_ctrl_jtag_errors	1.388m	3.135ms	20	20	100.00
		lc_ctrl_jtag_access	32.240s	11.004ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	38.230s	1.351ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	6.250s	1.163ms	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.920s	386.728us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	20.890s	3.648ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	11.100s	496.681us	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.090s	50.163us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	5.940s	909.047us	10	10	100.00
		lc_ctrl_jtag_alert_test	3.190s	108.932us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	17.650s	1.429ms	9	10	90.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.360s	81.908us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	10.357m	66.486ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.240s	22.056us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.850s	677.621us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.850s	677.621us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.130s	18.108us	5	5	100.00
		lc_ctrl_csr_rw	1.120s	112.852us	20	20	100.00
		lc_ctrl_csr_aliasing	1.730s	37.498us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.060s	49.118us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.130s	18.108us	5	5	100.00
		lc_ctrl_csr_rw	1.120s	112.852us	20	20	100.00
		lc_ctrl_csr_aliasing	1.730s	37.498us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.060s	49.118us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	38.460s	3.814ms	5	5	100.00
		lc_ctrl_tl_intg_err	4.230s	127.055us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.230s	127.055us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	26.860s	418.243us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	38.110s	359.963us	50	50	100.00
		lc_ctrl_sec_cm	38.460s	3.814ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	38.110s	359.963us	50	50	100.00
		lc_ctrl_sec_cm	38.460s	3.814ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	38.110s	359.963us	50	50	100.00
		lc_ctrl_sec_cm	38.460s	3.814ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	38.110s	359.963us	50	50	100.00
		lc_ctrl_sec_cm	38.460s	3.814ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	38.110s	359.963us	50	50	100.00
		lc_ctrl_sec_cm	38.460s	3.814ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	38.110s	359.963us	50	50	100.00
		lc_ctrl_sec_cm	38.460s	3.814ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	38.110s	359.963us	50	50	100.00
		lc_ctrl_sec_cm	38.460s	3.814ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	38.110s	359.963us	50	50	100.00
		lc_ctrl_sec_cm	38.460s	3.814ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	15.490s	1.519ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	9.600s	97.862us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	37.640s	1.408ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	29.420s	853.966us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	29.420s	853.966us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	21.260s	2.545ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	20.420s	620.105us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	20.420s	620.105us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	34.571m	28.747ms	23	50	46.00
V3		TOTAL			23	50	46.00
		TOTAL			1002	1030	97.28

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.86	97.89	95.50	93.31	97.67	98.55	99.00	96.11

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 24 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.12798578453238217135883885510520885432363830604114890359563083085073118752825
      Line 15783, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 14890271836 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 14890271836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.lc_ctrl_stress_all_with_rand_reset.80451152406947661952459586128981985708680263622514996879782911334249202104402
      Line 1391, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 16312730316 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 16312730316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 22 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 28.lc_ctrl_stress_all_with_rand_reset.45630006738831345898664689250403930387562435664917275667159039535745897851244
      Line 10038, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 57728397112 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 57728397112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 43.lc_ctrl_stress_all_with_rand_reset.59203267056600322830610501113635771606123609542143949903088849245228130331414
      Line 14232, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 10106849026 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 10106849026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (lc_ctrl_jtag_priority_vseq.sv:113) [lc_ctrl_jtag_priority_vseq] timeout occurred! has 1 failures:

  • Test lc_ctrl_jtag_priority has 1 failures.

    • 0.lc_ctrl_jtag_priority.41864990054962218237752042417568310272761948539458522279086975030211356062206
      Line 459, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_priority/latest/run.log

        UVM_FATAL @ 10016419542 ps: (lc_ctrl_jtag_priority_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.lc_ctrl_jtag_priority_vseq] timeout occurred!
        UVM_INFO @ 10016419542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_smoke_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_prog_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 6.lc_ctrl_stress_all_with_rand_reset.16914502937367218605847270459325176698336783712510984306312570930983299001417
      Line 35760, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 109759621055 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_smoke_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_prog_error fired unexpectedly!
        UVM_INFO @ 109759621055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
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