LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Thursday May 09 2024 19:02:32 UTC

GitHub Revision: 9656691e03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 30170103562476460183108208532025718695603957360441815475011549460912256789439

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	10.440s	153.463us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.360s	19.707us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.230s	19.729us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.010s	26.775us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.990s	42.745us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.820s	105.027us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.230s	19.729us	20	20	100.00
		lc_ctrl_csr_aliasing	1.990s	42.745us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	12.080s	664.422us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	30.170s	449.464us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.960s	11.087us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.230s	610.836us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	37.780s	420.237us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	21.760s	1.257ms	49	50	98.00
V2	security_escalation	lc_ctrl_state_failure	37.780s	420.237us	50	50	100.00
		lc_ctrl_prog_failure	4.230s	610.836us	50	50	100.00
		lc_ctrl_errors	21.760s	1.257ms	49	50	98.00
		lc_ctrl_security_escalation	14.900s	367.490us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.341m	2.201ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	18.330s	4.982ms	20	20	100.00
		lc_ctrl_jtag_errors	1.375m	3.006ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	14.160s	4.123ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	24.940s	2.881ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	18.330s	4.982ms	20	20	100.00
		lc_ctrl_jtag_errors	1.375m	3.006ms	20	20	100.00
		lc_ctrl_jtag_access	23.270s	1.029ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	38.970s	1.417ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	5.070s	770.141us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.850s	360.575us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	21.660s	1.891ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	14.070s	568.892us	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.630s	93.192us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	5.710s	204.216us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.650s	305.868us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	11.340s	3.638ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.250s	14.485us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	14.637m	25.268ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	2.000s	57.601us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.250s	584.062us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.250s	584.062us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.360s	19.707us	5	5	100.00
		lc_ctrl_csr_rw	1.230s	19.729us	20	20	100.00
		lc_ctrl_csr_aliasing	1.990s	42.745us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.930s	114.535us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.360s	19.707us	5	5	100.00
		lc_ctrl_csr_rw	1.230s	19.729us	20	20	100.00
		lc_ctrl_csr_aliasing	1.990s	42.745us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.930s	114.535us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	39.560s	460.400us	5	5	100.00
		lc_ctrl_tl_intg_err	3.530s	75.258us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	3.530s	75.258us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	30.170s	449.464us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	37.780s	420.237us	50	50	100.00
		lc_ctrl_sec_cm	39.560s	460.400us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	37.780s	420.237us	50	50	100.00
		lc_ctrl_sec_cm	39.560s	460.400us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	37.780s	420.237us	50	50	100.00
		lc_ctrl_sec_cm	39.560s	460.400us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	37.780s	420.237us	50	50	100.00
		lc_ctrl_sec_cm	39.560s	460.400us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	37.780s	420.237us	50	50	100.00
		lc_ctrl_sec_cm	39.560s	460.400us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	37.780s	420.237us	50	50	100.00
		lc_ctrl_sec_cm	39.560s	460.400us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	37.780s	420.237us	50	50	100.00
		lc_ctrl_sec_cm	39.560s	460.400us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	37.780s	420.237us	50	50	100.00
		lc_ctrl_sec_cm	39.560s	460.400us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	14.900s	367.490us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	12.080s	664.422us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	24.940s	2.881ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	29.380s	3.167ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	29.380s	3.167ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	20.090s	1.931ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	16.670s	547.735us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	16.670s	547.735us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	44.651m	26.712ms	21	50	42.00
V3		TOTAL			21	50	42.00
		TOTAL			1000	1030	97.09

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.90	97.89	95.59	93.31	97.67	98.55	99.00	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 26 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 26 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.47355492291085042521351613615639061601501673345670653543171641738626621057518
      Line 11148, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 25925629295 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10004 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 25925629295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.lc_ctrl_stress_all_with_rand_reset.112967000865025684408384037610514765663915598957165738644928450985535654534596
      Line 14040, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7282405584 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 7282405584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 24 more failures.

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 2.lc_ctrl_stress_all_with_rand_reset.93002351100673165979941924887345534166037185839739143228904407793034127332849
      Line 19314, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 13463956869 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 13463956869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 13.lc_ctrl_stress_all_with_rand_reset.81140116641335410601451865762364301058603999239858967147703420114792463285589
      Line 27905, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 122166834821 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 122166834821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 2 failures:

  • Test lc_ctrl_errors has 1 failures.

    • 10.lc_ctrl_errors.56957847659879310625224003904295733375687048176210243192804260730718692177776
      Line 1683, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_errors/latest/run.log

        UVM_ERROR @ 336603787 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 336603787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 20.lc_ctrl_stress_all_with_rand_reset.67229443940745173008324995212402903457997888242052893135451742406282807786467
      Line 5370, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 10037467999 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 10037467999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
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