LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Sunday May 12 2024 19:02:35 UTC

GitHub Revision: 69c572b503

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 72674276607041733394622960695970595070180537542023880499199659375034056632550

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	14.040s	801.238us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.330s	22.471us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.100s	16.579us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	3.250s	191.998us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.720s	196.001us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.060s	33.540us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.100s	16.579us	20	20	100.00
		lc_ctrl_csr_aliasing	1.720s	196.001us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.350s	124.175us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	23.610s	1.377ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.000s	13.924us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.790s	110.825us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	36.340s	1.748ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	26.640s	5.539ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	36.340s	1.748ms	50	50	100.00
		lc_ctrl_prog_failure	4.790s	110.825us	50	50	100.00
		lc_ctrl_errors	26.640s	5.539ms	50	50	100.00
		lc_ctrl_security_escalation	15.390s	793.890us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.545m	2.466ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	24.950s	961.769us	20	20	100.00
		lc_ctrl_jtag_errors	1.923m	4.341ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	11.200s	401.199us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	30.150s	3.471ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	24.950s	961.769us	20	20	100.00
		lc_ctrl_jtag_errors	1.923m	4.341ms	20	20	100.00
		lc_ctrl_jtag_access	28.650s	2.620ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	36.070s	2.705ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	4.650s	491.572us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.910s	1.333ms	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	47.260s	2.279ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	23.780s	2.129ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.510s	180.916us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.010s	1.126ms	10	10	100.00
		lc_ctrl_jtag_alert_test	2.080s	254.385us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	5.490s	723.501us	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.590s	58.944us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	7.922m	18.590ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.300s	153.176us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.970s	353.725us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.970s	353.725us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.330s	22.471us	5	5	100.00
		lc_ctrl_csr_rw	1.100s	16.579us	20	20	100.00
		lc_ctrl_csr_aliasing	1.720s	196.001us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.830s	94.495us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.330s	22.471us	5	5	100.00
		lc_ctrl_csr_rw	1.100s	16.579us	20	20	100.00
		lc_ctrl_csr_aliasing	1.720s	196.001us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.830s	94.495us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	25.130s	259.129us	5	5	100.00
		lc_ctrl_tl_intg_err	4.330s	224.893us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.330s	224.893us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	23.610s	1.377ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	36.340s	1.748ms	50	50	100.00
		lc_ctrl_sec_cm	25.130s	259.129us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	36.340s	1.748ms	50	50	100.00
		lc_ctrl_sec_cm	25.130s	259.129us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	36.340s	1.748ms	50	50	100.00
		lc_ctrl_sec_cm	25.130s	259.129us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	36.340s	1.748ms	50	50	100.00
		lc_ctrl_sec_cm	25.130s	259.129us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	36.340s	1.748ms	50	50	100.00
		lc_ctrl_sec_cm	25.130s	259.129us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	36.340s	1.748ms	50	50	100.00
		lc_ctrl_sec_cm	25.130s	259.129us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	36.340s	1.748ms	50	50	100.00
		lc_ctrl_sec_cm	25.130s	259.129us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	36.340s	1.748ms	50	50	100.00
		lc_ctrl_sec_cm	25.130s	259.129us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	15.390s	793.890us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.350s	124.175us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	30.150s	3.471ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	23.870s	1.602ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	23.870s	1.602ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	23.480s	1.121ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	19.590s	2.028ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	19.590s	2.028ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	31.421m	32.350ms	28	50	56.00
V3		TOTAL			28	50	56.00
		TOTAL			1007	1030	97.77

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.17	97.89	95.59	93.31	100.00	98.55	98.76	96.11

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 20 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.33581483062092812296697874177718750577250876880337504747350222090259402812837
      Line 8721, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6813391176 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 6813391176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.lc_ctrl_stress_all_with_rand_reset.22002303904213171455700488476739404311127336818746418879667532722747031245818
      Line 62006, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 32350079645 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 32350079645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 18 more failures.

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 10.lc_ctrl_stress_all_with_rand_reset.44484459709614489732266499942869855195799700067695598904598754803985688174378
      Line 33224, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 244585771673 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 244585771673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 22.lc_ctrl_stress_all_with_rand_reset.7387527868245964886076104828358924744438835729455536987277263993475121276688
      Line 38640, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 29729883515 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 29729883515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:

  • Test lc_ctrl_stress_all has 1 failures.

    • 47.lc_ctrl_stress_all.94543396011746327827655640186636540874003920737686699263808877406725539405008
      Line 4038, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 8055106161 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 8055106161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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