LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Tuesday May 14 2024 19:02:33 UTC

GitHub Revision: 00fe426038

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56275124637035941820967954627144971699378360917446801543187025394370981034792

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	7.510s	131.867us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.080s	173.163us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.120s	55.785us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.630s	66.904us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.330s	87.510us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.410s	32.105us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.120s	55.785us	20	20	100.00
		lc_ctrl_csr_aliasing	1.330s	87.510us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.760s	462.395us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	22.040s	331.766us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.990s	13.580us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	7.260s	178.338us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	38.350s	2.340ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	22.880s	2.174ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	38.350s	2.340ms	50	50	100.00
		lc_ctrl_prog_failure	7.260s	178.338us	50	50	100.00
		lc_ctrl_errors	22.880s	2.174ms	50	50	100.00
		lc_ctrl_security_escalation	16.960s	870.834us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.934m	3.599ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	11.330s	1.675ms	20	20	100.00
		lc_ctrl_jtag_errors	1.256m	5.545ms	19	20	95.00
V2	jtag_access	lc_ctrl_jtag_smoke	15.450s	2.805ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	25.720s	718.475us	20	20	100.00
		lc_ctrl_jtag_prog_failure	11.330s	1.675ms	20	20	100.00
		lc_ctrl_jtag_errors	1.256m	5.545ms	19	20	95.00
		lc_ctrl_jtag_access	18.760s	1.102ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	37.970s	1.276ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	2.930s	4.057ms	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.230s	276.341us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	23.720s	1.085ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	26.170s	4.905ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.940s	130.205us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	5.950s	203.308us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.790s	99.894us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	7.920s	2.415ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.340s	34.860us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	12.083m	88.671ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.640s	162.355us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.710s	310.857us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.710s	310.857us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.080s	173.163us	5	5	100.00
		lc_ctrl_csr_rw	1.120s	55.785us	20	20	100.00
		lc_ctrl_csr_aliasing	1.330s	87.510us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.910s	147.754us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.080s	173.163us	5	5	100.00
		lc_ctrl_csr_rw	1.120s	55.785us	20	20	100.00
		lc_ctrl_csr_aliasing	1.330s	87.510us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.910s	147.754us	20	20	100.00
V2		TOTAL			698	700	99.71
V2S	tl_intg_err	lc_ctrl_sec_cm	37.480s	203.364us	5	5	100.00
		lc_ctrl_tl_intg_err	4.450s	309.644us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.450s	309.644us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	22.040s	331.766us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	38.350s	2.340ms	50	50	100.00
		lc_ctrl_sec_cm	37.480s	203.364us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	38.350s	2.340ms	50	50	100.00
		lc_ctrl_sec_cm	37.480s	203.364us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	38.350s	2.340ms	50	50	100.00
		lc_ctrl_sec_cm	37.480s	203.364us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	38.350s	2.340ms	50	50	100.00
		lc_ctrl_sec_cm	37.480s	203.364us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	38.350s	2.340ms	50	50	100.00
		lc_ctrl_sec_cm	37.480s	203.364us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	38.350s	2.340ms	50	50	100.00
		lc_ctrl_sec_cm	37.480s	203.364us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	38.350s	2.340ms	50	50	100.00
		lc_ctrl_sec_cm	37.480s	203.364us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	38.350s	2.340ms	50	50	100.00
		lc_ctrl_sec_cm	37.480s	203.364us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	16.960s	870.834us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.760s	462.395us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	25.720s	718.475us	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	27.620s	976.035us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	27.620s	976.035us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	23.470s	660.300us	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	16.750s	2.115ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	16.750s	2.115ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	57.749m	68.654ms	22	50	44.00
V3		TOTAL			22	50	44.00
		TOTAL			1000	1030	97.09

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	25	92.59
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.28	97.89	96.13	93.31	100.00	98.55	99.00	96.11

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 23 failures.

    • 3.lc_ctrl_stress_all_with_rand_reset.53708458588851968139263826108819175749341935077500006386843285646224373908895
      Line 17545, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 19097722424 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 19097722424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 6.lc_ctrl_stress_all_with_rand_reset.97044873004740601324444673001444983156245058671029652217391318545786589629370
      Line 16641, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 9368693042 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 9368693042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 21 more failures.

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 4 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 4 failures.

    • 4.lc_ctrl_stress_all_with_rand_reset.107868833894551515319344974109049524270100407732163069655764456705950558229232
      Line 12586, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3181565676 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 3181565676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 13.lc_ctrl_stress_all_with_rand_reset.106439894370974814527188880494158076608917227457192347564768711973991598472180
      Line 27166, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 142069054551 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 142069054551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 2 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 2 failures:

  • Test lc_ctrl_stress_all has 1 failures.

    • 8.lc_ctrl_stress_all.100066780211203776290807330110882065871048685892003736061749648662551555800576
      Line 9524, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 7670780127 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 7670780127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 9.lc_ctrl_stress_all_with_rand_reset.95478371793688259571742429461089093308043161406000049539552893668301071232253
      Line 12135, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 109673409041 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 109673409041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_jtag_errors has 1 failures.

    • 3.lc_ctrl_jtag_errors.32293397752490603502235899658423939167506864850003891261330669301504309025837
      Line 804, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_errors/latest/run.log

        UVM_ERROR @ 727137548 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 727137548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.05.13_03.44.35
• 2024.05.10_04.31.37
• 2024.05.08_03.40.56
• 2024.05.06_04.57.29
• 2024.05.03_05.12.51
• 2024.05.01_04.24.15
• 2024.04.29_08.00.40