LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Thursday May 16 2024 19:02:11 UTC

GitHub Revision: 349bab6601

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 60729333463373082946889975499553948547086354767408862399987151421185145065082

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	8.700s	624.588us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.220s	36.165us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.070s	13.866us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.950s	204.911us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.370s	18.850us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.090s	28.420us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.070s	13.866us	20	20	100.00
		lc_ctrl_csr_aliasing	1.370s	18.850us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.930s	290.886us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	19.580s	292.075us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.960s	13.904us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.280s	641.149us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	34.270s	3.360ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	20.040s	3.348ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	34.270s	3.360ms	50	50	100.00
		lc_ctrl_prog_failure	5.280s	641.149us	50	50	100.00
		lc_ctrl_errors	20.040s	3.348ms	50	50	100.00
		lc_ctrl_security_escalation	14.290s	1.835ms	50	50	100.00
		lc_ctrl_jtag_state_failure	2.212m	18.322ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	13.460s	435.119us	20	20	100.00
		lc_ctrl_jtag_errors	1.414m	12.689ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	8.900s	3.921ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	24.870s	867.878us	20	20	100.00
		lc_ctrl_jtag_prog_failure	13.460s	435.119us	20	20	100.00
		lc_ctrl_jtag_errors	1.414m	12.689ms	20	20	100.00
		lc_ctrl_jtag_access	26.160s	10.936ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	40.700s	1.654ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	2.650s	84.131us	10	10	100.00
		lc_ctrl_jtag_csr_rw	4.000s	332.912us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	49.710s	2.272ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	19.130s	856.139us	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.030s	46.315us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	3.920s	126.822us	10	10	100.00
		lc_ctrl_jtag_alert_test	1.990s	59.962us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	9.990s	1.507ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.490s	26.846us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	11.156m	59.993ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.610s	42.241us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.440s	158.400us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.440s	158.400us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.220s	36.165us	5	5	100.00
		lc_ctrl_csr_rw	1.070s	13.866us	20	20	100.00
		lc_ctrl_csr_aliasing	1.370s	18.850us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.900s	42.235us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.220s	36.165us	5	5	100.00
		lc_ctrl_csr_rw	1.070s	13.866us	20	20	100.00
		lc_ctrl_csr_aliasing	1.370s	18.850us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.900s	42.235us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	23.750s	137.191us	5	5	100.00
		lc_ctrl_tl_intg_err	4.800s	435.029us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.800s	435.029us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	19.580s	292.075us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	34.270s	3.360ms	50	50	100.00
		lc_ctrl_sec_cm	23.750s	137.191us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	34.270s	3.360ms	50	50	100.00
		lc_ctrl_sec_cm	23.750s	137.191us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	34.270s	3.360ms	50	50	100.00
		lc_ctrl_sec_cm	23.750s	137.191us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	34.270s	3.360ms	50	50	100.00
		lc_ctrl_sec_cm	23.750s	137.191us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	34.270s	3.360ms	50	50	100.00
		lc_ctrl_sec_cm	23.750s	137.191us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	34.270s	3.360ms	50	50	100.00
		lc_ctrl_sec_cm	23.750s	137.191us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	34.270s	3.360ms	50	50	100.00
		lc_ctrl_sec_cm	23.750s	137.191us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	34.270s	3.360ms	50	50	100.00
		lc_ctrl_sec_cm	23.750s	137.191us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	14.290s	1.835ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.930s	290.886us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	24.870s	867.878us	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	24.740s	530.663us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	24.740s	530.663us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	25.750s	4.615ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	15.380s	1.906ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	15.380s	1.906ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.768h	141.225ms	22	50	44.00
V3		TOTAL			22	50	44.00
		TOTAL			1001	1030	97.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.92	97.89	95.95	93.31	97.67	98.55	98.76	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 23 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.79862283249408478785907833860108554639821963659435534447617858718194718934878
      Line 6488, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 17456842465 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 17456842465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.lc_ctrl_stress_all_with_rand_reset.112653531923786967848757517938890982793696340998338101097952330580817218380779
      Line 12594, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 53937022059 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 53937022059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 21 more failures.

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.25780549624870924595100496400487812377665698218255045843665254585033363341786
      Line 30653, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 58905174069 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 58905174069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 29.lc_ctrl_stress_all_with_rand_reset.16271498911769901591832848156117678697199608571994383889334262112206334883207
      Line 25829, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 10915522164 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 10915522164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 27.lc_ctrl_stress_all_with_rand_reset.13699599957650249907313131415247696386567086509872466999265764698614135728241
      Line 43831, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 141225498416 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 141225498416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 35.lc_ctrl_stress_all_with_rand_reset.112590721006314851798167029863273103576569779777590564257281626814230440484057
      Line 6329, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5644222943 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 5644222943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 30.lc_ctrl_stress_all_with_rand_reset.14092135180153534657110808543453877035558917206893359638418277605765983038834
      Line 42600, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_stress_all has 1 failures.

    • 32.lc_ctrl_stress_all.112078578017365996527670641603931914323662080718892136619662107360590963473535
      Line 365, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 269269980 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 269269980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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