LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Sunday May 19 2024 19:02:23 UTC

GitHub Revision: eb776817a5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56458776725427632834749451790671712939002859133119076946547796163671543192855

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	9.230s	336.549us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.090s	27.529us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.180s	20.010us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.630s	64.444us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.660s	144.505us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.840s	22.400us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.180s	20.010us	20	20	100.00
		lc_ctrl_csr_aliasing	1.660s	144.505us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	12.090s	565.056us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	23.300s	1.909ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.920s	19.058us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.680s	143.283us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	33.800s	873.762us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	23.300s	554.985us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	33.800s	873.762us	50	50	100.00
		lc_ctrl_prog_failure	5.680s	143.283us	50	50	100.00
		lc_ctrl_errors	23.300s	554.985us	50	50	100.00
		lc_ctrl_security_escalation	17.620s	503.280us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.511m	10.992ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	26.430s	3.683ms	20	20	100.00
		lc_ctrl_jtag_errors	2.074m	11.585ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	20.950s	3.249ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	31.060s	1.939ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	26.430s	3.683ms	20	20	100.00
		lc_ctrl_jtag_errors	2.074m	11.585ms	20	20	100.00
		lc_ctrl_jtag_access	32.960s	1.433ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	38.980s	1.336ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.330s	234.443us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.510s	80.064us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	45.830s	9.242ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	28.560s	1.399ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.160s	48.800us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	5.360s	865.339us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.360s	138.704us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	39.980s	1.800ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.170s	16.898us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	10.458m	45.636ms	48	50	96.00
V2	alert_test	lc_ctrl_alert_test	1.360s	29.130us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.080s	774.222us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.080s	774.222us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.090s	27.529us	5	5	100.00
		lc_ctrl_csr_rw	1.180s	20.010us	20	20	100.00
		lc_ctrl_csr_aliasing	1.660s	144.505us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.110s	58.617us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.090s	27.529us	5	5	100.00
		lc_ctrl_csr_rw	1.180s	20.010us	20	20	100.00
		lc_ctrl_csr_aliasing	1.660s	144.505us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.110s	58.617us	20	20	100.00
V2		TOTAL			698	700	99.71
V2S	tl_intg_err	lc_ctrl_sec_cm	41.620s	1.645ms	5	5	100.00
		lc_ctrl_tl_intg_err	6.170s	204.949us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	6.170s	204.949us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	23.300s	1.909ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	33.800s	873.762us	50	50	100.00
		lc_ctrl_sec_cm	41.620s	1.645ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	33.800s	873.762us	50	50	100.00
		lc_ctrl_sec_cm	41.620s	1.645ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	33.800s	873.762us	50	50	100.00
		lc_ctrl_sec_cm	41.620s	1.645ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	33.800s	873.762us	50	50	100.00
		lc_ctrl_sec_cm	41.620s	1.645ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	33.800s	873.762us	50	50	100.00
		lc_ctrl_sec_cm	41.620s	1.645ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	33.800s	873.762us	50	50	100.00
		lc_ctrl_sec_cm	41.620s	1.645ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	33.800s	873.762us	50	50	100.00
		lc_ctrl_sec_cm	41.620s	1.645ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	33.800s	873.762us	50	50	100.00
		lc_ctrl_sec_cm	41.620s	1.645ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	17.620s	503.280us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	12.090s	565.056us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	31.060s	1.939ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	22.380s	549.265us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	22.380s	549.265us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	25.130s	659.419us	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	14.500s	1.450ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	14.500s	1.450ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.766h	65.910ms	16	50	32.00
V3		TOTAL			16	50	32.00
		TOTAL			994	1030	96.50

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.16	97.89	95.95	93.31	100.00	98.55	98.51	95.94

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 25 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 25 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.40000632886625068684992650990337919880927965737377255642131253692039051007758
      Line 11333, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 50027165217 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 50027165217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.lc_ctrl_stress_all_with_rand_reset.82334741541146129170574139435689265258426316933384963220477366676504747341084
      Line 19522, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 9448164395 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 9448164395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 23 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 4 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 2.lc_ctrl_stress_all_with_rand_reset.95070580222172334317613602485441681102618580003797986439556404999637388314232
      Line 14314, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 23072370294 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 23072370294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 32.lc_ctrl_stress_all_with_rand_reset.102002530002215522156006234779694678517202636851172317033638640115133020498417
      Line 21658, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 22132747269 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 22132747269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

  • Test lc_ctrl_stress_all has 1 failures.

    • 41.lc_ctrl_stress_all.109549429366126961091057198857627069449852107522025918524552964552389902396705
      Line 16081, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 37631044744 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 37631044744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 3 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 34.lc_ctrl_stress_all_with_rand_reset.36930276502154495940239350352239928967323243006785771452031887967282699600626
      Line 37166, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 127694767994 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 127694767994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 42.lc_ctrl_stress_all_with_rand_reset.86759972575245545541469258123512172051493960653044302339265369938028187007892
      Line 22326, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 52133873631 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 52133873631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• Error-[CNST-STOF] Constraint solver timeout failure has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 24.lc_ctrl_stress_all_with_rand_reset.65317194089503981031126270001149721449274979924237781318584593580285223814742
      Line 41895, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • 38.lc_ctrl_stress_all_with_rand_reset.55994072619598506498235888201234656483836726571258455417907695319046175638622
      Line 38328, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• Job lc_ctrl_volatile_unlock_enabled-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 3.lc_ctrl_stress_all_with_rand_reset.90990917989794565333153986299129738540620435487251575942221904480249018708000
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:50cf0743-5846-44f7-b14a-aa335a7fd177
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_stress_all has 1 failures.

    • 22.lc_ctrl_stress_all.78010844780861055444577726712552903727495939565496771517506434780212263748643
      Line 2824, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 448374978 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 448374978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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