LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Tuesday May 21 2024 19:02:35 UTC

GitHub Revision: be3d980075

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85829748320245376283659198434338498577935164172956485671224275001047693479661

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	11.070s	222.507us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.150s	15.563us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.030s	39.426us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.840s	724.870us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.860s	39.975us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.990s	24.795us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.030s	39.426us	20	20	100.00
		lc_ctrl_csr_aliasing	1.860s	39.975us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.800s	87.132us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	21.850s	780.380us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.970s	62.034us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.440s	357.654us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	35.100s	832.593us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	23.580s	3.433ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	35.100s	832.593us	50	50	100.00
		lc_ctrl_prog_failure	4.440s	357.654us	50	50	100.00
		lc_ctrl_errors	23.580s	3.433ms	50	50	100.00
		lc_ctrl_security_escalation	16.280s	393.844us	50	50	100.00
		lc_ctrl_jtag_state_failure	2.394m	4.618ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	15.680s	590.676us	20	20	100.00
		lc_ctrl_jtag_errors	1.486m	12.931ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	11.250s	1.741ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	35.890s	8.230ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	15.680s	590.676us	20	20	100.00
		lc_ctrl_jtag_errors	1.486m	12.931ms	20	20	100.00
		lc_ctrl_jtag_access	18.690s	4.175ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	37.580s	1.434ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	4.510s	1.533ms	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.750s	290.372us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	17.840s	2.688ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	26.330s	2.325ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.850s	447.487us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	5.160s	2.325ms	10	10	100.00
		lc_ctrl_jtag_alert_test	1.750s	234.494us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	54.550s	14.155ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.340s	144.947us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	7.275m	17.037ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.680s	42.383us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.250s	280.392us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.250s	280.392us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.150s	15.563us	5	5	100.00
		lc_ctrl_csr_rw	1.030s	39.426us	20	20	100.00
		lc_ctrl_csr_aliasing	1.860s	39.975us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.990s	47.621us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.150s	15.563us	5	5	100.00
		lc_ctrl_csr_rw	1.030s	39.426us	20	20	100.00
		lc_ctrl_csr_aliasing	1.860s	39.975us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.990s	47.621us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	41.930s	7.510ms	5	5	100.00
		lc_ctrl_tl_intg_err	5.780s	627.168us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	5.780s	627.168us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	21.850s	780.380us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	35.100s	832.593us	50	50	100.00
		lc_ctrl_sec_cm	41.930s	7.510ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	35.100s	832.593us	50	50	100.00
		lc_ctrl_sec_cm	41.930s	7.510ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	35.100s	832.593us	50	50	100.00
		lc_ctrl_sec_cm	41.930s	7.510ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	35.100s	832.593us	50	50	100.00
		lc_ctrl_sec_cm	41.930s	7.510ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	35.100s	832.593us	50	50	100.00
		lc_ctrl_sec_cm	41.930s	7.510ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	35.100s	832.593us	50	50	100.00
		lc_ctrl_sec_cm	41.930s	7.510ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	35.100s	832.593us	50	50	100.00
		lc_ctrl_sec_cm	41.930s	7.510ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	35.100s	832.593us	50	50	100.00
		lc_ctrl_sec_cm	41.930s	7.510ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	16.280s	393.844us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.800s	87.132us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	35.890s	8.230ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	28.630s	674.326us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	28.630s	674.326us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	21.520s	1.234ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	22.610s	720.855us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	22.610s	720.855us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	2.162h	120.941ms	27	50	54.00
V3		TOTAL			27	50	54.00
		TOTAL			1006	1030	97.67

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.98	97.89	96.13	93.31	97.67	98.55	99.00	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 19 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 19 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.41475617778344628038679424469294167302329965975240157324184520579011013482266
      Line 40232, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 101144992711 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 101144992711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.lc_ctrl_stress_all_with_rand_reset.67634011495967287152673050467585214747555342083710525110128783570487405485102
      Line 1166, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 19936083799 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 19936083799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 17 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 4 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 23.lc_ctrl_stress_all_with_rand_reset.45354918612220912267537903115382494437449593944468854566602068153845487595824
      Line 26728, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 34793912758 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 34793912758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 24.lc_ctrl_stress_all_with_rand_reset.36647134553656921998442780265202830878019358870119226185585309162275889652044
      Line 15358, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 76703170063 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 76703170063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

  • Test lc_ctrl_stress_all has 1 failures.

    • 24.lc_ctrl_stress_all.45632419502438244804876525267328251959092773148390000469347194646861333144163
      Line 6450, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 8055187089 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 8055187089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 22.lc_ctrl_stress_all_with_rand_reset.17114201258542649590624857386957944531516706780716021144780631700262488911319
      Line 40244, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 63143674043 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 63143674043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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