LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Thursday May 23 2024 19:02:32 UTC

GitHub Revision: 1579f6a912

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107680075914347604077716278187232582575581754843183664337576824686885697334979

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	9.570s	797.986us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.180s	18.291us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.170s	18.418us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.220s	583.684us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.760s	152.976us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.990s	87.108us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.170s	18.418us	20	20	100.00
		lc_ctrl_csr_aliasing	1.760s	152.976us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	9.810s	108.233us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	20.900s	328.075us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.940s	51.622us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.710s	111.748us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	36.550s	533.443us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	23.200s	8.442ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	36.550s	533.443us	50	50	100.00
		lc_ctrl_prog_failure	4.710s	111.748us	50	50	100.00
		lc_ctrl_errors	23.200s	8.442ms	50	50	100.00
		lc_ctrl_security_escalation	16.330s	3.255ms	50	50	100.00
		lc_ctrl_jtag_state_failure	2.084m	70.605ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	19.170s	2.466ms	20	20	100.00
		lc_ctrl_jtag_errors	2.064m	4.857ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	15.420s	2.301ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	24.980s	597.644us	20	20	100.00
		lc_ctrl_jtag_prog_failure	19.170s	2.466ms	20	20	100.00
		lc_ctrl_jtag_errors	2.064m	4.857ms	20	20	100.00
		lc_ctrl_jtag_access	25.250s	1.075ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	36.340s	2.574ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	6.160s	322.497us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.320s	461.261us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	39.370s	15.777ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	17.360s	1.227ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.920s	41.365us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	7.660s	1.368ms	10	10	100.00
		lc_ctrl_jtag_alert_test	2.040s	61.142us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	30.560s	16.008ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.600s	56.032us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	9.561m	70.941ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.260s	25.483us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.950s	158.900us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.950s	158.900us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.180s	18.291us	5	5	100.00
		lc_ctrl_csr_rw	1.170s	18.418us	20	20	100.00
		lc_ctrl_csr_aliasing	1.760s	152.976us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.850s	174.265us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.180s	18.291us	5	5	100.00
		lc_ctrl_csr_rw	1.170s	18.418us	20	20	100.00
		lc_ctrl_csr_aliasing	1.760s	152.976us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.850s	174.265us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	41.670s	233.320us	5	5	100.00
		lc_ctrl_tl_intg_err	5.290s	338.265us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	5.290s	338.265us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	20.900s	328.075us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	36.550s	533.443us	50	50	100.00
		lc_ctrl_sec_cm	41.670s	233.320us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	36.550s	533.443us	50	50	100.00
		lc_ctrl_sec_cm	41.670s	233.320us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	36.550s	533.443us	50	50	100.00
		lc_ctrl_sec_cm	41.670s	233.320us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	36.550s	533.443us	50	50	100.00
		lc_ctrl_sec_cm	41.670s	233.320us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	36.550s	533.443us	50	50	100.00
		lc_ctrl_sec_cm	41.670s	233.320us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	36.550s	533.443us	50	50	100.00
		lc_ctrl_sec_cm	41.670s	233.320us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	36.550s	533.443us	50	50	100.00
		lc_ctrl_sec_cm	41.670s	233.320us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	36.550s	533.443us	50	50	100.00
		lc_ctrl_sec_cm	41.670s	233.320us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	16.330s	3.255ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	9.810s	108.233us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	24.980s	597.644us	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	21.460s	3.252ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	21.460s	3.252ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	24.410s	4.714ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	17.220s	848.524us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	17.220s	848.524us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.796h	49.763ms	21	50	42.00
V3		TOTAL			21	50	42.00
		TOTAL			1001	1030	97.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.82	97.89	95.68	93.31	97.67	98.55	98.51	96.11

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 24 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.39548473097146185949036382675593970087816177738583519661917253632041673395764
      Line 32972, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 138945612866 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 138945612866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 7.lc_ctrl_stress_all_with_rand_reset.18140464206499000198764472424416127655584159992071901970194534044883879504120
      Line 29950, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 159038677475 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 159038677475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 22 more failures.

• Error-[CNST-STOF] Constraint solver timeout failure has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 2.lc_ctrl_stress_all_with_rand_reset.73272064552275243762538580244435024233371916054209315179488648975719022283493
      Line 66713, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • 8.lc_ctrl_stress_all_with_rand_reset.100290569499347418823626677760046789610419463346745379784520938428291884980407
      Line 38825, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 35.lc_ctrl_stress_all_with_rand_reset.57397494118876813051479320559480588463100234005556527941969550169525137876896
      Line 45399, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 203813665041 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 203813665041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 49.lc_ctrl_stress_all_with_rand_reset.16409001986720444842428686749426669491799289720826461594208490329482810382143
      Line 53659, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 78246142691 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 78246142691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 6.lc_ctrl_stress_all_with_rand_reset.5314580718995434905471190366150383322449098098253099825893628747778409799932
      Line 17600, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 20846704340 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 20846704340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
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