LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Sunday May 26 2024 19:04:10 UTC

GitHub Revision: 2cf28c40e5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 76231542290686940289653487239061276463019235878731279188279352215076078972419

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	10.220s	504.712us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.260s	20.868us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.170s	18.178us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.000s	93.752us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.630s	408.162us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.250s	65.045us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.170s	18.178us	20	20	100.00
		lc_ctrl_csr_aliasing	1.630s	408.162us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	12.140s	259.898us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	24.260s	3.090ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.980s	12.347us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.730s	161.062us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	34.930s	554.031us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	29.560s	706.644us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	34.930s	554.031us	50	50	100.00
		lc_ctrl_prog_failure	4.730s	161.062us	50	50	100.00
		lc_ctrl_errors	29.560s	706.644us	50	50	100.00
		lc_ctrl_security_escalation	18.550s	2.386ms	50	50	100.00
		lc_ctrl_jtag_state_failure	2.137m	15.801ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	19.360s	3.539ms	20	20	100.00
		lc_ctrl_jtag_errors	1.180m	6.260ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	11.880s	452.406us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	28.270s	3.302ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	19.360s	3.539ms	20	20	100.00
		lc_ctrl_jtag_errors	1.180m	6.260ms	20	20	100.00
		lc_ctrl_jtag_access	20.310s	13.743ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	35.250s	1.163ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.670s	269.380us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.180s	214.851us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	31.680s	12.953ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	13.650s	1.130ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.540s	179.902us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	6.800s	1.070ms	10	10	100.00
		lc_ctrl_jtag_alert_test	2.690s	92.631us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	11.650s	1.944ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.370s	22.835us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	11.206m	21.740ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.430s	293.991us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.020s	133.372us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.020s	133.372us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.260s	20.868us	5	5	100.00
		lc_ctrl_csr_rw	1.170s	18.178us	20	20	100.00
		lc_ctrl_csr_aliasing	1.630s	408.162us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.030s	253.510us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.260s	20.868us	5	5	100.00
		lc_ctrl_csr_rw	1.170s	18.178us	20	20	100.00
		lc_ctrl_csr_aliasing	1.630s	408.162us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.030s	253.510us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	40.250s	208.922us	5	5	100.00
		lc_ctrl_tl_intg_err	4.040s	422.377us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.040s	422.377us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	24.260s	3.090ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	34.930s	554.031us	50	50	100.00
		lc_ctrl_sec_cm	40.250s	208.922us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	34.930s	554.031us	50	50	100.00
		lc_ctrl_sec_cm	40.250s	208.922us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	34.930s	554.031us	50	50	100.00
		lc_ctrl_sec_cm	40.250s	208.922us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	34.930s	554.031us	50	50	100.00
		lc_ctrl_sec_cm	40.250s	208.922us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	34.930s	554.031us	50	50	100.00
		lc_ctrl_sec_cm	40.250s	208.922us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	34.930s	554.031us	50	50	100.00
		lc_ctrl_sec_cm	40.250s	208.922us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	34.930s	554.031us	50	50	100.00
		lc_ctrl_sec_cm	40.250s	208.922us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	34.930s	554.031us	50	50	100.00
		lc_ctrl_sec_cm	40.250s	208.922us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	18.550s	2.386ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	12.140s	259.898us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	28.270s	3.302ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	29.440s	2.842ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	29.440s	2.842ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	22.170s	1.575ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	16.200s	585.878us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	16.200s	585.878us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.188h	101.297ms	19	50	38.00
V3		TOTAL			19	50	38.00
		TOTAL			999	1030	96.99

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.25	97.89	95.95	93.31	100.00	98.55	98.76	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 24 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.87256826622102255068501952062902754926209560568402851047509604607970275769932
      Line 21891, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 54653046148 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 54653046148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.lc_ctrl_stress_all_with_rand_reset.16483220245885306481640916860946761022009776831560490578771934385938605420978
      Line 40491, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 184414047772 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 184414047772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 22 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 3 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 16.lc_ctrl_stress_all_with_rand_reset.87603031927705587559119915234714030597020007835194022053378744383122713155787
      Line 9200, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 8010725073 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 8010725073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 32.lc_ctrl_stress_all_with_rand_reset.72102362551943093653350632606516555037393268433608962173180735711275595530728
      Line 13188, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 92666392254 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 92666392254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• Error-[CNST-STOF] Constraint solver timeout failure has 3 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 19.lc_ctrl_stress_all_with_rand_reset.54298856663484509379037992558898250097462460375400417793448239779054165358662
      Line 39866, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • 21.lc_ctrl_stress_all_with_rand_reset.75051899907701388230742674196274481709680907924943618556250215812396510829043
      Line 43860, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • ... and 1 more failures.

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 49.lc_ctrl_stress_all_with_rand_reset.79419226032716992392336482768336792131916625070179942181126342214824956750281
      Line 24524, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 13296695311 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 13296695311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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