LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Tuesday May 28 2024 19:30:06 UTC

GitHub Revision: 0e5093d709

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 51604449886868634540233838791789448907774502353938218657919214072353062987195

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	11.570s	779.083us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.230s	20.432us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.130s	13.725us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.960s	28.451us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.540s	328.971us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.510s	32.524us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.130s	13.725us	20	20	100.00
		lc_ctrl_csr_aliasing	1.540s	328.971us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	11.800s	333.808us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	21.940s	390.955us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.000s	23.818us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	6.330s	649.060us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	37.080s	354.164us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	28.150s	3.458ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	37.080s	354.164us	50	50	100.00
		lc_ctrl_prog_failure	6.330s	649.060us	50	50	100.00
		lc_ctrl_errors	28.150s	3.458ms	50	50	100.00
		lc_ctrl_security_escalation	15.980s	458.882us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.411m	14.859ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	29.560s	2.183ms	20	20	100.00
		lc_ctrl_jtag_errors	1.345m	2.840ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	14.050s	3.151ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	29.340s	3.835ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	29.560s	2.183ms	20	20	100.00
		lc_ctrl_jtag_errors	1.345m	2.840ms	20	20	100.00
		lc_ctrl_jtag_access	22.880s	4.680ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	35.200s	2.574ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.810s	538.310us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.680s	335.399us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	29.300s	2.679ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	12.430s	496.597us	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.880s	49.604us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.810s	618.955us	10	10	100.00
		lc_ctrl_jtag_alert_test	3.140s	744.369us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	22.300s	9.953ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.210s	14.752us	49	50	98.00
V2	stress_all	lc_ctrl_stress_all	9.163m	17.909ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.410s	95.556us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.170s	136.994us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.170s	136.994us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.230s	20.432us	5	5	100.00
		lc_ctrl_csr_rw	1.130s	13.725us	20	20	100.00
		lc_ctrl_csr_aliasing	1.540s	328.971us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.000s	92.562us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.230s	20.432us	5	5	100.00
		lc_ctrl_csr_rw	1.130s	13.725us	20	20	100.00
		lc_ctrl_csr_aliasing	1.540s	328.971us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.000s	92.562us	20	20	100.00
V2		TOTAL			698	700	99.71
V2S	tl_intg_err	lc_ctrl_sec_cm	40.180s	1.628ms	5	5	100.00
		lc_ctrl_tl_intg_err	4.440s	128.371us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.440s	128.371us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	21.940s	390.955us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	37.080s	354.164us	50	50	100.00
		lc_ctrl_sec_cm	40.180s	1.628ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	37.080s	354.164us	50	50	100.00
		lc_ctrl_sec_cm	40.180s	1.628ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	37.080s	354.164us	50	50	100.00
		lc_ctrl_sec_cm	40.180s	1.628ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	37.080s	354.164us	50	50	100.00
		lc_ctrl_sec_cm	40.180s	1.628ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	37.080s	354.164us	50	50	100.00
		lc_ctrl_sec_cm	40.180s	1.628ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	37.080s	354.164us	50	50	100.00
		lc_ctrl_sec_cm	40.180s	1.628ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	37.080s	354.164us	50	50	100.00
		lc_ctrl_sec_cm	40.180s	1.628ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	37.080s	354.164us	50	50	100.00
		lc_ctrl_sec_cm	40.180s	1.628ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	15.980s	458.882us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.800s	333.808us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	29.340s	3.835ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	24.250s	856.601us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	24.250s	856.601us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	26.000s	1.203ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	16.730s	801.153us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	16.730s	801.153us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	56.142m	77.466ms	19	50	38.00
V3		TOTAL			19	50	38.00
		TOTAL			997	1030	96.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	25	92.59
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.20	97.89	95.50	93.31	100.00	98.55	98.51	96.64

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 22 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 22 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.82338066073260623889217492594877251513240360177070652720336714427055748939041
      Line 12548, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5298509614 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 5298509614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.lc_ctrl_stress_all_with_rand_reset.79455300069419929322433158083266971822616216884008217898909521717928536179744
      Line 4297, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6999476694 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 6999476694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 20 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 3 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.74518894056147386129975878015250801559995375990694392231329641985014305473808
      Line 26732, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 27014059937 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 27014059937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 15.lc_ctrl_stress_all_with_rand_reset.54341162687469065726174078041682372743452004899832282805359504181302284630565
      Line 5210, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5626707337 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 5626707337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• Error-[CNST-STOF] Constraint solver timeout failure has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 2.lc_ctrl_stress_all_with_rand_reset.81461640628386399500593939957582739802906744462865951751036094234564011667102
      Line 46574, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • 25.lc_ctrl_stress_all_with_rand_reset.101671405954313140726034712894202119644345399778425123764880142169673956244048
      Line 42247, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 17.lc_ctrl_stress_all_with_rand_reset.25479298031423642667913405764849958874373433642344207626984307604456831856895
      Line 19217, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 36389261380 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 36389261380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 37.lc_ctrl_stress_all_with_rand_reset.69446155437765484514586569208838729430084056202747998519051644691277082116488
      Line 34403, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 25650521070 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 25650521070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 30.lc_ctrl_stress_all_with_rand_reset.89873194246450513777809795404256582472777260847469008619125645336175967988988
      Line 23223, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 19738166314 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 19738166314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_stress_all has 1 failures.

    • 49.lc_ctrl_stress_all.6112239192222429670082135236910411720569423721589337286091599214254989167492
      Line 5344, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 6241354955 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 6241354955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout lc_ctrl_reg_block.status.transition_successful (addr=*) == * has 1 failures:

  • Test lc_ctrl_volatile_unlock_smoke has 1 failures.

    • 25.lc_ctrl_volatile_unlock_smoke.111413084222628186679260997884033699150791281055196121750060117212324408750210
      Line 323, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_volatile_unlock_smoke/latest/run.log

        UVM_FATAL @ 126725110 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout lc_ctrl_reg_block.status.transition_successful (addr=0x86b13c04) == 0x1
        UVM_INFO @ 126725110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:753) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 44.lc_ctrl_stress_all_with_rand_reset.67015514036279020435587158620530598334848590338103686863172787689716625539669
      Line 18265, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 89934572560 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 89934572560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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