LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Thursday May 30 2024 19:02:59 UTC

GitHub Revision: 8cb25a6867

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 26638040090898561482658723926798947801831709189350919955228328310045202344042

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	9.600s	1.033ms	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.250s	37.869us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.140s	17.495us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.840s	28.795us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.640s	65.236us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.050s	90.087us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.140s	17.495us	20	20	100.00
		lc_ctrl_csr_aliasing	1.640s	65.236us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	11.490s	321.549us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	27.440s	2.664ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.010s	23.469us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.350s	324.258us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	39.920s	343.435us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	29.000s	845.581us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	39.920s	343.435us	50	50	100.00
		lc_ctrl_prog_failure	4.350s	324.258us	50	50	100.00
		lc_ctrl_errors	29.000s	845.581us	50	50	100.00
		lc_ctrl_security_escalation	16.980s	2.698ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.901m	7.555ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	25.710s	932.868us	20	20	100.00
		lc_ctrl_jtag_errors	1.993m	21.118ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	16.080s	5.804ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	26.040s	1.835ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	25.710s	932.868us	20	20	100.00
		lc_ctrl_jtag_errors	1.993m	21.118ms	20	20	100.00
		lc_ctrl_jtag_access	26.980s	1.102ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	39.400s	6.536ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	6.060s	328.548us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.450s	86.567us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	27.440s	1.289ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	16.550s	2.856ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.030s	47.242us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	3.770s	399.823us	10	10	100.00
		lc_ctrl_jtag_alert_test	1.790s	195.617us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	1.073m	3.005ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.220s	16.102us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	14.195m	26.930ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.260s	75.228us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.070s	517.872us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.070s	517.872us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.250s	37.869us	5	5	100.00
		lc_ctrl_csr_rw	1.140s	17.495us	20	20	100.00
		lc_ctrl_csr_aliasing	1.640s	65.236us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.000s	498.309us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.250s	37.869us	5	5	100.00
		lc_ctrl_csr_rw	1.140s	17.495us	20	20	100.00
		lc_ctrl_csr_aliasing	1.640s	65.236us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.000s	498.309us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	32.040s	453.465us	5	5	100.00
		lc_ctrl_tl_intg_err	5.490s	1.666ms	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	5.490s	1.666ms	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	27.440s	2.664ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	39.920s	343.435us	50	50	100.00
		lc_ctrl_sec_cm	32.040s	453.465us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	39.920s	343.435us	50	50	100.00
		lc_ctrl_sec_cm	32.040s	453.465us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	39.920s	343.435us	50	50	100.00
		lc_ctrl_sec_cm	32.040s	453.465us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	39.920s	343.435us	50	50	100.00
		lc_ctrl_sec_cm	32.040s	453.465us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	39.920s	343.435us	50	50	100.00
		lc_ctrl_sec_cm	32.040s	453.465us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	39.920s	343.435us	50	50	100.00
		lc_ctrl_sec_cm	32.040s	453.465us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	39.920s	343.435us	50	50	100.00
		lc_ctrl_sec_cm	32.040s	453.465us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	39.920s	343.435us	50	50	100.00
		lc_ctrl_sec_cm	32.040s	453.465us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	16.980s	2.698ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.490s	321.549us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	26.040s	1.835ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	28.160s	1.390ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	28.160s	1.390ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	22.950s	3.146ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	24.200s	1.086ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	24.200s	1.086ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.167h	44.006ms	18	50	36.00
V3		TOTAL			18	50	36.00
		TOTAL			998	1030	96.89

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.23	97.89	95.77	93.31	100.00	98.55	99.00	96.11

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 28 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 28 failures.

    • 2.lc_ctrl_stress_all_with_rand_reset.113719355900765815711062191268353535157801508974725724526863099818531516283635
      Line 30538, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 35985868575 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 35985868575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.lc_ctrl_stress_all_with_rand_reset.5927293727215756688110712205246608647027676198033283205107194006414139354528
      Line 8565, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 10336072106 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 10336072106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 26 more failures.

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 5.lc_ctrl_stress_all_with_rand_reset.39218354811646656815650813731212317301479709337234162545248215230481598355045
      Line 23870, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 80668865846 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 80668865846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 42.lc_ctrl_stress_all_with_rand_reset.36987968585443994470709526960413014502707746546184858874457985855477712977722
      Line 8538, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 25866902214 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 25866902214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 36.lc_ctrl_stress_all_with_rand_reset.88562206173180159147375096045601019097618569259717914722665675579201860046777
      Line 29320, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 39.lc_ctrl_stress_all_with_rand_reset.38744294282421072345774264542880718289545905864386299541300421684392410672537
      Line 7518, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 10822491519 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 10822491519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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