LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Sunday June 02 2024 19:02:53 UTC

GitHub Revision: 01a208901a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 50418669159766293903157726892781832882154091083197082086235277423705989875584

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	13.010s	267.209us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.090s	17.396us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.150s	19.360us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.880s	25.979us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.640s	33.275us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.150s	125.857us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.150s	19.360us	20	20	100.00
		lc_ctrl_csr_aliasing	1.640s	33.275us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.060s	118.699us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	22.520s	519.295us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.970s	13.603us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.760s	509.041us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	41.070s	336.959us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	26.640s	1.796ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	41.070s	336.959us	50	50	100.00
		lc_ctrl_prog_failure	4.760s	509.041us	50	50	100.00
		lc_ctrl_errors	26.640s	1.796ms	50	50	100.00
		lc_ctrl_security_escalation	14.990s	784.153us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.585m	3.140ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	20.020s	3.192ms	20	20	100.00
		lc_ctrl_jtag_errors	1.706m	7.252ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	18.630s	2.927ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	24.930s	2.924ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	20.020s	3.192ms	20	20	100.00
		lc_ctrl_jtag_errors	1.706m	7.252ms	20	20	100.00
		lc_ctrl_jtag_access	19.800s	803.972us	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	32.320s	4.307ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	5.070s	207.063us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.930s	569.367us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	43.750s	2.069ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	13.600s	2.829ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.760s	58.389us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.500s	147.558us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.860s	393.025us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	30.310s	2.964ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.570s	40.215us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	12.643m	94.551ms	48	50	96.00
V2	alert_test	lc_ctrl_alert_test	1.670s	501.855us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.090s	391.325us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.090s	391.325us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.090s	17.396us	5	5	100.00
		lc_ctrl_csr_rw	1.150s	19.360us	20	20	100.00
		lc_ctrl_csr_aliasing	1.640s	33.275us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.210s	49.269us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.090s	17.396us	5	5	100.00
		lc_ctrl_csr_rw	1.150s	19.360us	20	20	100.00
		lc_ctrl_csr_aliasing	1.640s	33.275us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.210s	49.269us	20	20	100.00
V2		TOTAL			698	700	99.71
V2S	tl_intg_err	lc_ctrl_sec_cm	25.020s	113.497us	5	5	100.00
		lc_ctrl_tl_intg_err	4.510s	515.429us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.510s	515.429us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	22.520s	519.295us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	41.070s	336.959us	50	50	100.00
		lc_ctrl_sec_cm	25.020s	113.497us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	41.070s	336.959us	50	50	100.00
		lc_ctrl_sec_cm	25.020s	113.497us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	41.070s	336.959us	50	50	100.00
		lc_ctrl_sec_cm	25.020s	113.497us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	41.070s	336.959us	50	50	100.00
		lc_ctrl_sec_cm	25.020s	113.497us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	41.070s	336.959us	50	50	100.00
		lc_ctrl_sec_cm	25.020s	113.497us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	41.070s	336.959us	50	50	100.00
		lc_ctrl_sec_cm	25.020s	113.497us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	41.070s	336.959us	50	50	100.00
		lc_ctrl_sec_cm	25.020s	113.497us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	41.070s	336.959us	50	50	100.00
		lc_ctrl_sec_cm	25.020s	113.497us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	14.990s	784.153us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.060s	118.699us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	24.930s	2.924ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	18.980s	1.646ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	18.980s	1.646ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	19.450s	1.713ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	17.940s	2.753ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	17.940s	2.753ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	2.380h	83.713ms	16	50	32.00
V3		TOTAL			16	50	32.00
		TOTAL			994	1030	96.50

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.81	97.89	95.50	93.31	97.67	98.55	98.26	96.47

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 31 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 31 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.38520180848366539980368905155093133019594503368479346348595633674418156055595
      Line 19453, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 32790053693 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 32790053693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.lc_ctrl_stress_all_with_rand_reset.63232344272826301697484005513096236489489050902987536095392819894465708877955
      Line 12806, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 13779866167 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 13779866167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 29 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 3 failures:

  • Test lc_ctrl_stress_all has 1 failures.

    • 6.lc_ctrl_stress_all.54333194808795038593633776960448795726651955816751518492789501241587027009376
      Line 7058, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 70062230322 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 70062230322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 41.lc_ctrl_stress_all_with_rand_reset.20708160210861008230482852631589294911049934964843250926992430928245352956295
      Line 7486, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 22399927766 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 22399927766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 48.lc_ctrl_stress_all_with_rand_reset.97455086857001177936654613437464161776501463995781952434889413427626580734732
      Line 636, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1587005857 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 1587005857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 2 failures:

  • Test lc_ctrl_stress_all has 1 failures.

    • 10.lc_ctrl_stress_all.65847869866348083214571860091633466946509781904858209629311344894177509607389
      Line 2180, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 10780638451 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 10780638451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 17.lc_ctrl_stress_all_with_rand_reset.102781253889982480285511886815618189670714613549730501996641953273877975852045
      Line 32662, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 68333879163 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 68333879163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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