LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Tuesday June 04 2024 19:02:20 UTC

GitHub Revision: a182fcef27

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 115716131103921631007013649731972014580281041353363476420230431751664670300928

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	10.890s	775.025us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.060s	20.990us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.060s	14.451us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.550s	70.379us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.420s	25.166us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.110s	150.395us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.060s	14.451us	20	20	100.00
		lc_ctrl_csr_aliasing	1.420s	25.166us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	9.540s	191.502us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	18.340s	2.198ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.930s	11.175us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.620s	427.195us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	37.390s	351.759us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	22.160s	562.340us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	37.390s	351.759us	50	50	100.00
		lc_ctrl_prog_failure	4.620s	427.195us	50	50	100.00
		lc_ctrl_errors	22.160s	562.340us	50	50	100.00
		lc_ctrl_security_escalation	16.050s	532.105us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.267m	22.116ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	16.520s	2.149ms	20	20	100.00
		lc_ctrl_jtag_errors	1.716m	4.056ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	14.580s	2.066ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	26.530s	4.256ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	16.520s	2.149ms	20	20	100.00
		lc_ctrl_jtag_errors	1.716m	4.056ms	20	20	100.00
		lc_ctrl_jtag_access	24.300s	4.892ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	31.050s	1.890ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	4.630s	319.583us	10	10	100.00
		lc_ctrl_jtag_csr_rw	4.040s	577.255us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	21.820s	8.088ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	9.660s	3.456ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.740s	69.813us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	5.350s	343.354us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.100s	248.851us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	21.200s	3.639ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.400s	19.624us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	5.868m	10.146ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.590s	141.854us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	3.330s	2.211ms	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	3.330s	2.211ms	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.060s	20.990us	5	5	100.00
		lc_ctrl_csr_rw	1.060s	14.451us	20	20	100.00
		lc_ctrl_csr_aliasing	1.420s	25.166us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.920s	50.758us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.060s	20.990us	5	5	100.00
		lc_ctrl_csr_rw	1.060s	14.451us	20	20	100.00
		lc_ctrl_csr_aliasing	1.420s	25.166us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.920s	50.758us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	41.480s	261.794us	5	5	100.00
		lc_ctrl_tl_intg_err	4.200s	119.876us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.200s	119.876us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	18.340s	2.198ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	37.390s	351.759us	50	50	100.00
		lc_ctrl_sec_cm	41.480s	261.794us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	37.390s	351.759us	50	50	100.00
		lc_ctrl_sec_cm	41.480s	261.794us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	37.390s	351.759us	50	50	100.00
		lc_ctrl_sec_cm	41.480s	261.794us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	37.390s	351.759us	50	50	100.00
		lc_ctrl_sec_cm	41.480s	261.794us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	37.390s	351.759us	50	50	100.00
		lc_ctrl_sec_cm	41.480s	261.794us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	37.390s	351.759us	50	50	100.00
		lc_ctrl_sec_cm	41.480s	261.794us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	37.390s	351.759us	50	50	100.00
		lc_ctrl_sec_cm	41.480s	261.794us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	37.390s	351.759us	50	50	100.00
		lc_ctrl_sec_cm	41.480s	261.794us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	16.050s	532.105us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	9.540s	191.502us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	26.530s	4.256ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	27.680s	13.743ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	27.680s	13.743ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	26.460s	1.067ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	16.910s	1.262ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	16.910s	1.262ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	2.728h	202.179ms	23	50	46.00
V3		TOTAL			23	50	46.00
		TOTAL			1002	1030	97.28

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.24	97.89	95.68	93.31	100.00	98.55	98.76	96.47

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 23 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.78042158119843847812470828359075383212734990863249087101252783201108103599494
      Line 6502, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 17491394517 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 17491394517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.lc_ctrl_stress_all_with_rand_reset.102604068173674581242089689738243472751392036413979806826921949236433541222530
      Line 26478, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 89206371758 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 89206371758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 21 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 3 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 33.lc_ctrl_stress_all_with_rand_reset.50067408350448210432430272022316876131921051941162890259421883927405048256950
      Line 10298, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3331022366 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 3331022366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 36.lc_ctrl_stress_all_with_rand_reset.2477326722731964723506941736822347533066409123319029746694386255723766820222
      Line 4949, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 26942864983 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 26942864983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_stress_all has 1 failures.

    • 36.lc_ctrl_stress_all.18882459639813789850164562318374467130568032978341845660293821150704000721336
      Line 2353, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 53420403957 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 53420403957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 9.lc_ctrl_stress_all_with_rand_reset.72204707466756087825444039360636518651301232745245299125021317491975005979048
      Line 36572, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 39036512821 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 39036512821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 41.lc_ctrl_stress_all_with_rand_reset.49439127230373088197297248287313095892400856699817467623664086179748712451664
      Line 8337, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 26472915147 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 26472915147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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