LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Wednesday June 05 2024 22:14:46 UTC

GitHub Revision: b29ffbb03c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 104714960319679935410420483500971829136303708457300037460974663680452494898918

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	11.420s	705.153us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.060s	18.150us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.200s	26.764us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	3.310s	364.611us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.770s	35.680us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.720s	52.773us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.200s	26.764us	20	20	100.00
		lc_ctrl_csr_aliasing	1.770s	35.680us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	11.020s	657.401us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	18.770s	282.908us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.930s	33.598us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.070s	2.392ms	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	35.390s	1.553ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	25.770s	1.963ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	35.390s	1.553ms	50	50	100.00
		lc_ctrl_prog_failure	5.070s	2.392ms	50	50	100.00
		lc_ctrl_errors	25.770s	1.963ms	50	50	100.00
		lc_ctrl_security_escalation	17.560s	1.880ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.663m	8.806ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	16.580s	12.373ms	20	20	100.00
		lc_ctrl_jtag_errors	1.476m	13.511ms	19	20	95.00
V2	jtag_access	lc_ctrl_jtag_smoke	16.120s	1.179ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	28.980s	3.801ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	16.580s	12.373ms	20	20	100.00
		lc_ctrl_jtag_errors	1.476m	13.511ms	19	20	95.00
		lc_ctrl_jtag_access	23.600s	4.099ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	36.510s	1.208ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	6.050s	1.007ms	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.460s	200.360us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	49.660s	4.016ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	13.020s	2.043ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.090s	200.291us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.280s	136.986us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.610s	440.626us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	19.000s	2.870ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.710s	28.331us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	8.645m	67.907ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.410s	28.899us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.070s	2.055ms	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.070s	2.055ms	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.060s	18.150us	5	5	100.00
		lc_ctrl_csr_rw	1.200s	26.764us	20	20	100.00
		lc_ctrl_csr_aliasing	1.770s	35.680us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.030s	511.692us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.060s	18.150us	5	5	100.00
		lc_ctrl_csr_rw	1.200s	26.764us	20	20	100.00
		lc_ctrl_csr_aliasing	1.770s	35.680us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.030s	511.692us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	43.510s	470.813us	5	5	100.00
		lc_ctrl_tl_intg_err	4.900s	172.204us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.900s	172.204us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	18.770s	282.908us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	35.390s	1.553ms	50	50	100.00
		lc_ctrl_sec_cm	43.510s	470.813us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	35.390s	1.553ms	50	50	100.00
		lc_ctrl_sec_cm	43.510s	470.813us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	35.390s	1.553ms	50	50	100.00
		lc_ctrl_sec_cm	43.510s	470.813us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	35.390s	1.553ms	50	50	100.00
		lc_ctrl_sec_cm	43.510s	470.813us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	35.390s	1.553ms	50	50	100.00
		lc_ctrl_sec_cm	43.510s	470.813us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	35.390s	1.553ms	50	50	100.00
		lc_ctrl_sec_cm	43.510s	470.813us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	35.390s	1.553ms	50	50	100.00
		lc_ctrl_sec_cm	43.510s	470.813us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	35.390s	1.553ms	50	50	100.00
		lc_ctrl_sec_cm	43.510s	470.813us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	17.560s	1.880ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.020s	657.401us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	28.980s	3.801ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	21.050s	474.208us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	21.050s	474.208us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	31.860s	1.759ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	17.080s	498.636us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	17.080s	498.636us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	32.103m	21.754ms	20	50	40.00
V3		TOTAL			20	50	40.00
		TOTAL			999	1030	96.99

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.88	97.89	95.68	93.31	97.67	98.55	98.76	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 25 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 25 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.108026985280302914269225755935314652354980009530955613077289888965452022578160
      Line 67100, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 160671856553 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 160671856553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 5.lc_ctrl_stress_all_with_rand_reset.93218697424619417431374009972671589890012886235230051674133170730384210682229
      Line 32696, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 108901572655 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 108901572655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 23 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 2 failures:

  • Test lc_ctrl_jtag_errors has 1 failures.

    • 9.lc_ctrl_jtag_errors.82118045954822507314623490642905220244979450114439555761435444983663999655493
      Line 3147, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_errors/latest/run.log

        UVM_ERROR @ 2988735600 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 2988735600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 49.lc_ctrl_stress_all_with_rand_reset.112855113628074168737571294592503264451534882405404889998614653265196492684885
      Line 627, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 569647658 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 569647658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 24.lc_ctrl_stress_all_with_rand_reset.29656133882436470471035341086867014821884743315289782749041910496576792270750
      Line 49486, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 536061930539 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 536061930539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 39.lc_ctrl_stress_all_with_rand_reset.60585464586328637320275441969669245109569798635951999818948588147545852026235
      Line 39373, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 69867283187 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 69867283187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 35.lc_ctrl_stress_all_with_rand_reset.6148851871917822035323210781292123829838225636396417395218873282560953301647
      Line 13941, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 136884487940 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 136884487940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job lc_ctrl_volatile_unlock_enabled-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 41.lc_ctrl_stress_all_with_rand_reset.55748549824156957161232886130743939311787850585662192034394566203484971548176
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:690a69a4-aba7-4566-a551-9cb743a9c646
      

Past Results

• Latest
• 2024.06.05_03.52.14
• 2024.06.03_06.55.11
• 2024.05.31_04.47.10
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• 2024.05.27_04.23.31
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