LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Thursday June 06 2024 19:04:47 UTC

GitHub Revision: 32d52b8d41

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 59908589074363629542901507660786833114562191729708937078847065421241135561861

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	11.240s	1.145ms	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.120s	15.301us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.070s	13.904us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.020s	176.407us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.730s	65.373us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.000s	26.539us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.070s	13.904us	20	20	100.00
		lc_ctrl_csr_aliasing	1.730s	65.373us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	11.770s	104.773us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	18.830s	322.652us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.000s	13.738us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.650s	110.927us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	33.810s	602.942us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	24.840s	665.220us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	33.810s	602.942us	50	50	100.00
		lc_ctrl_prog_failure	4.650s	110.927us	50	50	100.00
		lc_ctrl_errors	24.840s	665.220us	50	50	100.00
		lc_ctrl_security_escalation	18.580s	545.306us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.313m	8.459ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	27.690s	1.090ms	20	20	100.00
		lc_ctrl_jtag_errors	1.859m	4.127ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	18.020s	646.145us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	21.770s	2.063ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	27.690s	1.090ms	20	20	100.00
		lc_ctrl_jtag_errors	1.859m	4.127ms	20	20	100.00
		lc_ctrl_jtag_access	25.710s	4.413ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	37.400s	8.711ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	4.730s	186.313us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.160s	621.728us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	45.710s	2.197ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	22.800s	2.326ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.860s	86.618us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	6.000s	924.026us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.720s	85.187us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	34.080s	3.101ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.170s	90.120us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	12.389m	194.101ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.500s	61.046us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.310s	112.756us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.310s	112.756us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.120s	15.301us	5	5	100.00
		lc_ctrl_csr_rw	1.070s	13.904us	20	20	100.00
		lc_ctrl_csr_aliasing	1.730s	65.373us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.990s	42.803us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.120s	15.301us	5	5	100.00
		lc_ctrl_csr_rw	1.070s	13.904us	20	20	100.00
		lc_ctrl_csr_aliasing	1.730s	65.373us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.990s	42.803us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	48.770s	1.224ms	5	5	100.00
		lc_ctrl_tl_intg_err	4.000s	448.462us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.000s	448.462us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	18.830s	322.652us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	33.810s	602.942us	50	50	100.00
		lc_ctrl_sec_cm	48.770s	1.224ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	33.810s	602.942us	50	50	100.00
		lc_ctrl_sec_cm	48.770s	1.224ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	33.810s	602.942us	50	50	100.00
		lc_ctrl_sec_cm	48.770s	1.224ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	33.810s	602.942us	50	50	100.00
		lc_ctrl_sec_cm	48.770s	1.224ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	33.810s	602.942us	50	50	100.00
		lc_ctrl_sec_cm	48.770s	1.224ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	33.810s	602.942us	50	50	100.00
		lc_ctrl_sec_cm	48.770s	1.224ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	33.810s	602.942us	50	50	100.00
		lc_ctrl_sec_cm	48.770s	1.224ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	33.810s	602.942us	50	50	100.00
		lc_ctrl_sec_cm	48.770s	1.224ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	18.580s	545.306us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.770s	104.773us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	21.770s	2.063ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	23.710s	615.589us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	23.710s	615.589us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	27.550s	3.559ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	23.520s	1.417ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	23.520s	1.417ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	2.684h	95.944ms	19	50	38.00
V3		TOTAL			19	50	38.00
		TOTAL			999	1030	96.99

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.20	97.89	95.59	93.31	100.00	98.55	98.76	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 27 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 27 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.65387886334311060562236984937612901380953994961587990176000109342747369724612
      Line 23544, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 38482939527 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 38482939527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.lc_ctrl_stress_all_with_rand_reset.38601601404508163612649557796615774917129179986561093130241075445411807020995
      Line 341, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1906673130 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1906673130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 25 more failures.

• Error-[CNST-STOF] Constraint solver timeout failure has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 11.lc_ctrl_stress_all_with_rand_reset.41706516496508936866326307589624464518837590627893517491160309833498264888298
      Line 35047, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • 20.lc_ctrl_stress_all_with_rand_reset.33755073435164086038210293786154824016877280150410041419103940265181905095569
      Line 29117, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 19.lc_ctrl_stress_all_with_rand_reset.104084213699729742104016502554483877397961815091421776917473456620171561881134
      Line 22477, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 74710277960 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 74710277960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 34.lc_ctrl_stress_all_with_rand_reset.77684029070688547274873627955796611751748046187720646073968307262511476112822
      Line 35000, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 123557773753 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 123557773753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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