LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Saturday June 08 2024 00:41:57 UTC

GitHub Revision: 302b24f3c6

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 32491226968592963393132943636196950930602503490106290691157604759716956925599

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	10.670s	649.729us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.120s	27.278us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.070s	27.151us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.070s	65.736us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.430s	33.573us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.160s	26.031us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.070s	27.151us	20	20	100.00
		lc_ctrl_csr_aliasing	1.430s	33.573us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.790s	74.059us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	22.850s	422.181us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.000s	17.661us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	6.290s	797.732us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	34.530s	1.258ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	24.230s	2.049ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	34.530s	1.258ms	50	50	100.00
		lc_ctrl_prog_failure	6.290s	797.732us	50	50	100.00
		lc_ctrl_errors	24.230s	2.049ms	50	50	100.00
		lc_ctrl_security_escalation	19.440s	4.526ms	50	50	100.00
		lc_ctrl_jtag_state_failure	2.084m	30.695ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	21.160s	738.895us	20	20	100.00
		lc_ctrl_jtag_errors	1.523m	6.503ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	15.330s	2.508ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	31.370s	1.786ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	21.160s	738.895us	20	20	100.00
		lc_ctrl_jtag_errors	1.523m	6.503ms	20	20	100.00
		lc_ctrl_jtag_access	21.850s	1.808ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	37.500s	1.276ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	4.340s	655.613us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.380s	1.037ms	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	49.400s	23.697ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	20.730s	3.897ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.110s	155.353us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	5.180s	747.966us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.690s	656.398us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	12.110s	1.274ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.490s	41.665us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	14.743m	55.971ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.410s	21.612us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	3.990s	844.406us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	3.990s	844.406us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.120s	27.278us	5	5	100.00
		lc_ctrl_csr_rw	1.070s	27.151us	20	20	100.00
		lc_ctrl_csr_aliasing	1.430s	33.573us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.500s	22.693us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.120s	27.278us	5	5	100.00
		lc_ctrl_csr_rw	1.070s	27.151us	20	20	100.00
		lc_ctrl_csr_aliasing	1.430s	33.573us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.500s	22.693us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	40.000s	404.875us	5	5	100.00
		lc_ctrl_tl_intg_err	4.560s	554.979us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.560s	554.979us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	22.850s	422.181us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	34.530s	1.258ms	50	50	100.00
		lc_ctrl_sec_cm	40.000s	404.875us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	34.530s	1.258ms	50	50	100.00
		lc_ctrl_sec_cm	40.000s	404.875us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	34.530s	1.258ms	50	50	100.00
		lc_ctrl_sec_cm	40.000s	404.875us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	34.530s	1.258ms	50	50	100.00
		lc_ctrl_sec_cm	40.000s	404.875us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	34.530s	1.258ms	50	50	100.00
		lc_ctrl_sec_cm	40.000s	404.875us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	34.530s	1.258ms	50	50	100.00
		lc_ctrl_sec_cm	40.000s	404.875us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	34.530s	1.258ms	50	50	100.00
		lc_ctrl_sec_cm	40.000s	404.875us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	34.530s	1.258ms	50	50	100.00
		lc_ctrl_sec_cm	40.000s	404.875us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	19.440s	4.526ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.790s	74.059us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	31.370s	1.786ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	20.140s	2.937ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	20.140s	2.937ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	23.510s	2.299ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	19.670s	2.390ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	19.670s	2.390ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	32.162m	158.371ms	18	50	36.00
V3		TOTAL			18	50	36.00
		TOTAL			997	1030	96.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.93	97.89	95.68	93.34	97.67	98.55	98.76	96.64

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 26 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 26 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.102942163016492620809528710312043855861639852332575457443232668606361779935989
      Line 26253, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 54161921524 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 54161921524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.lc_ctrl_stress_all_with_rand_reset.32380124814157802916121977165626751826515186986333900194294129393262882681534
      Line 30481, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 43669314700 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 43669314700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 24 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 6 failures:

  • Test lc_ctrl_stress_all has 1 failures.

    • 12.lc_ctrl_stress_all.41443293206425755511124610650140129384906256559715632816718121971575838309718
      Line 1276, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 7651243264 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 7651243264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_stress_all_with_rand_reset has 5 failures.

    • 17.lc_ctrl_stress_all_with_rand_reset.12821895622752254520896892339681405621491297943743292372498377132903156937457
      Line 10692, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1200262655 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 1200262655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 27.lc_ctrl_stress_all_with_rand_reset.76035488491336721530691462027516637360533102315161007221040066305754004795762
      Line 21899, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 15507816856 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 15507816856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 3 more failures.

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 42.lc_ctrl_stress_all_with_rand_reset.41874815402533084914216153009998401723572959752010418206924781441450797359181
      Line 11953, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 23337188404 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 23337188404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
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