LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Sunday June 09 2024 19:02:32 UTC

GitHub Revision: f92a5ee77b

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 74888572473032497941251936200792687439223302665780333354656685678472336958420

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	11.460s	407.111us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.260s	70.803us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.150s	29.277us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	3.150s	185.799us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.400s	33.869us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.860s	24.591us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.150s	29.277us	20	20	100.00
		lc_ctrl_csr_aliasing	1.400s	33.869us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.380s	151.807us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	22.480s	1.299ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.010s	11.474us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.910s	108.374us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	37.950s	381.181us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	22.740s	1.164ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	37.950s	381.181us	50	50	100.00
		lc_ctrl_prog_failure	4.910s	108.374us	50	50	100.00
		lc_ctrl_errors	22.740s	1.164ms	50	50	100.00
		lc_ctrl_security_escalation	15.350s	2.868ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.418m	18.234ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	20.450s	3.219ms	20	20	100.00
		lc_ctrl_jtag_errors	1.344m	5.627ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	16.190s	2.517ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	24.840s	4.588ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	20.450s	3.219ms	20	20	100.00
		lc_ctrl_jtag_errors	1.344m	5.627ms	20	20	100.00
		lc_ctrl_jtag_access	27.820s	1.401ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	37.860s	4.867ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.890s	131.685us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.180s	126.857us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	19.880s	1.508ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	15.840s	2.628ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.650s	266.977us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	3.670s	1.982ms	10	10	100.00
		lc_ctrl_jtag_alert_test	2.210s	75.073us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	18.780s	1.988ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.170s	18.408us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	7.518m	87.225ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.320s	26.435us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	3.490s	138.056us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	3.490s	138.056us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.260s	70.803us	5	5	100.00
		lc_ctrl_csr_rw	1.150s	29.277us	20	20	100.00
		lc_ctrl_csr_aliasing	1.400s	33.869us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.030s	131.835us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.260s	70.803us	5	5	100.00
		lc_ctrl_csr_rw	1.150s	29.277us	20	20	100.00
		lc_ctrl_csr_aliasing	1.400s	33.869us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.030s	131.835us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	42.100s	270.943us	5	5	100.00
		lc_ctrl_tl_intg_err	4.020s	649.288us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.020s	649.288us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	22.480s	1.299ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	37.950s	381.181us	50	50	100.00
		lc_ctrl_sec_cm	42.100s	270.943us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	37.950s	381.181us	50	50	100.00
		lc_ctrl_sec_cm	42.100s	270.943us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	37.950s	381.181us	50	50	100.00
		lc_ctrl_sec_cm	42.100s	270.943us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	37.950s	381.181us	50	50	100.00
		lc_ctrl_sec_cm	42.100s	270.943us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	37.950s	381.181us	50	50	100.00
		lc_ctrl_sec_cm	42.100s	270.943us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	37.950s	381.181us	50	50	100.00
		lc_ctrl_sec_cm	42.100s	270.943us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	37.950s	381.181us	50	50	100.00
		lc_ctrl_sec_cm	42.100s	270.943us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	37.950s	381.181us	50	50	100.00
		lc_ctrl_sec_cm	42.100s	270.943us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	15.350s	2.868ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.380s	151.807us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	24.840s	4.588ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	28.990s	1.616ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	28.990s	1.616ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	26.560s	2.384ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	19.450s	1.146ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	19.450s	1.146ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.366h	122.230ms	24	50	48.00
V3		TOTAL			24	50	48.00
		TOTAL			1004	1030	97.48

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.22	97.89	95.68	93.34	100.00	98.55	99.00	96.11

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 20 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.109999464213084381416611471027754993794809366193629393866135032421409759855055
      Line 25551, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 45837163881 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 45837163881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.lc_ctrl_stress_all_with_rand_reset.105650001632907865271073536170008759820841799052073954321863937354972943150977
      Line 25644, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 43493432134 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 43493432134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 18 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 3 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 23.lc_ctrl_stress_all_with_rand_reset.90710938427771440386306376351465726152615299360582811494890207396255589016727
      Line 40933, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 120222775212 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 120222775212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 35.lc_ctrl_stress_all_with_rand_reset.44775016454677603684723886198996362309007096668526247649333065133214338120287
      Line 8045, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 20098800544 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 20098800544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• Error-[CNST-STOF] Constraint solver timeout failure has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 34.lc_ctrl_stress_all_with_rand_reset.73670171689798147105272313171047197778969627244289898940380374399374928192176
      Line 39146, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • 47.lc_ctrl_stress_all_with_rand_reset.56146631426203469551888123935720338379462039684792283448467094797525187618244
      Line 35427, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 2.lc_ctrl_stress_all_with_rand_reset.44974367021782656132014914613608793955324127392749984402516917669619630662843
      Line 45064, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 22288707383 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 22288707383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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