LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Monday June 10 2024 23:28:43 UTC

GitHub Revision: a8c9c17a8c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 72227341233107832543509484606850665418885932500709631655793413524197290927900

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	7.610s	214.873us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.110s	22.409us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.120s	17.836us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	3.130s	384.301us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.330s	35.956us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.200s	104.563us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.120s	17.836us	20	20	100.00
		lc_ctrl_csr_aliasing	1.330s	35.956us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.170s	87.318us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	20.070s	350.199us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.030s	13.706us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.040s	281.368us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	33.210s	348.111us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	25.370s	648.620us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	33.210s	348.111us	50	50	100.00
		lc_ctrl_prog_failure	5.040s	281.368us	50	50	100.00
		lc_ctrl_errors	25.370s	648.620us	50	50	100.00
		lc_ctrl_security_escalation	17.620s	1.167ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.866m	11.761ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	31.120s	20.021ms	20	20	100.00
		lc_ctrl_jtag_errors	1.488m	3.321ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	10.500s	1.313ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	36.010s	1.250ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	31.120s	20.021ms	20	20	100.00
		lc_ctrl_jtag_errors	1.488m	3.321ms	20	20	100.00
		lc_ctrl_jtag_access	17.890s	2.480ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	40.040s	2.855ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	5.680s	366.431us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.490s	1.259ms	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	30.710s	10.449ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	14.320s	3.699ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.190s	99.549us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.010s	864.693us	10	10	100.00
		lc_ctrl_jtag_alert_test	1.410s	71.326us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	12.540s	1.402ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.370s	20.791us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	8.038m	15.000ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.390s	96.949us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.440s	757.725us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.440s	757.725us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.110s	22.409us	5	5	100.00
		lc_ctrl_csr_rw	1.120s	17.836us	20	20	100.00
		lc_ctrl_csr_aliasing	1.330s	35.956us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.960s	514.151us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.110s	22.409us	5	5	100.00
		lc_ctrl_csr_rw	1.120s	17.836us	20	20	100.00
		lc_ctrl_csr_aliasing	1.330s	35.956us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.960s	514.151us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	41.580s	743.998us	5	5	100.00
		lc_ctrl_tl_intg_err	4.500s	109.557us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.500s	109.557us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	20.070s	350.199us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	33.210s	348.111us	50	50	100.00
		lc_ctrl_sec_cm	41.580s	743.998us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	33.210s	348.111us	50	50	100.00
		lc_ctrl_sec_cm	41.580s	743.998us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	33.210s	348.111us	50	50	100.00
		lc_ctrl_sec_cm	41.580s	743.998us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	33.210s	348.111us	50	50	100.00
		lc_ctrl_sec_cm	41.580s	743.998us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	33.210s	348.111us	50	50	100.00
		lc_ctrl_sec_cm	41.580s	743.998us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	33.210s	348.111us	50	50	100.00
		lc_ctrl_sec_cm	41.580s	743.998us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	33.210s	348.111us	50	50	100.00
		lc_ctrl_sec_cm	41.580s	743.998us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	33.210s	348.111us	50	50	100.00
		lc_ctrl_sec_cm	41.580s	743.998us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	17.620s	1.167ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.170s	87.318us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	36.010s	1.250ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	29.660s	1.671ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	29.660s	1.671ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	26.610s	3.361ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	27.270s	9.526ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	27.270s	9.526ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	24.579m	61.782ms	20	50	40.00
V3		TOTAL			20	50	40.00
		TOTAL			999	1030	96.99

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.23	97.89	95.77	93.34	100.00	98.55	98.76	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 23 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.108062124208116650809663460160933236348322712440526536850645747122216708209186
      Line 15670, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 58934939011 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 58934939011 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.lc_ctrl_stress_all_with_rand_reset.85171935771656915790598179815151307705750917471614011129687910999426562878204
      Line 16396, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 113532505973 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 113532505973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 21 more failures.

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 3 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 9.lc_ctrl_stress_all_with_rand_reset.7824940976989414827897620224334857433545532305298655511189240318269302594434
      Line 29544, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 42103544154 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 42103544154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 21.lc_ctrl_stress_all_with_rand_reset.3406935355318544728765379693483856568378835145160225584128899933010187952797
      Line 14269, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 26972362046 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 26972362046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 5.lc_ctrl_stress_all_with_rand_reset.33029292319172706170474594646251183392084786960410947428559818269347166076974
      Line 565, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 390249959 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 390249959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 47.lc_ctrl_stress_all_with_rand_reset.13225891693482276672960076583248972584965364757096176278800845149634638547710
      Line 13720, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 96243288599 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 96243288599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 18.lc_ctrl_stress_all_with_rand_reset.86841560116963806036866933085869336821337595083923537315419239524135869876081
      Line 41822, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 80039733403 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 80039733403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 33.lc_ctrl_stress_all_with_rand_reset.79307095873307803113319353734276197330327022080843011196335556758479968957789
      Line 30226, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:769) [lc_ctrl_lc_errors_vseq] Check failed otp_error_act == otp_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_stress_all has 1 failures.

    • 47.lc_ctrl_stress_all.31087839032223891077242141407946580504811104750479263507576034463364351446122
      Line 13118, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 6567320835 ps: (lc_ctrl_errors_vseq.sv:769) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed otp_error_act == otp_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 6567320835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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