LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Tuesday June 11 2024 19:02:38 UTC

GitHub Revision: dd5ad5fb77

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 66418170746903624595625818392428707033482455256751560525176982524210226376736

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	4.510s	319.133us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.280s	20.018us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.130s	18.531us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	3.180s	97.514us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.430s	45.980us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.640s	29.703us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.130s	18.531us	20	20	100.00
		lc_ctrl_csr_aliasing	1.430s	45.980us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	13.350s	458.641us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	19.650s	352.287us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.920s	19.337us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.160s	172.763us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	36.920s	266.519us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	23.530s	632.050us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	36.920s	266.519us	50	50	100.00
		lc_ctrl_prog_failure	5.160s	172.763us	50	50	100.00
		lc_ctrl_errors	23.530s	632.050us	50	50	100.00
		lc_ctrl_security_escalation	15.450s	1.707ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.612m	14.013ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	19.030s	1.274ms	20	20	100.00
		lc_ctrl_jtag_errors	2.126m	4.865ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	15.090s	637.605us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	27.530s	6.217ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	19.030s	1.274ms	20	20	100.00
		lc_ctrl_jtag_errors	2.126m	4.865ms	20	20	100.00
		lc_ctrl_jtag_access	16.910s	716.401us	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	40.140s	8.415ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	4.760s	775.200us	10	10	100.00
		lc_ctrl_jtag_csr_rw	4.200s	605.533us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	27.260s	1.244ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	28.660s	1.302ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.900s	40.956us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	5.130s	1.032ms	10	10	100.00
		lc_ctrl_jtag_alert_test	2.910s	311.882us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	7.380s	278.032us	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.320s	55.827us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	11.872m	35.771ms	48	50	96.00
V2	alert_test	lc_ctrl_alert_test	1.810s	93.224us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.450s	298.645us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.450s	298.645us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.280s	20.018us	5	5	100.00
		lc_ctrl_csr_rw	1.130s	18.531us	20	20	100.00
		lc_ctrl_csr_aliasing	1.430s	45.980us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.920s	86.342us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.280s	20.018us	5	5	100.00
		lc_ctrl_csr_rw	1.130s	18.531us	20	20	100.00
		lc_ctrl_csr_aliasing	1.430s	45.980us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.920s	86.342us	20	20	100.00
V2		TOTAL			698	700	99.71
V2S	tl_intg_err	lc_ctrl_sec_cm	39.970s	2.616ms	5	5	100.00
		lc_ctrl_tl_intg_err	5.170s	623.902us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	5.170s	623.902us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	19.650s	352.287us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	36.920s	266.519us	50	50	100.00
		lc_ctrl_sec_cm	39.970s	2.616ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	36.920s	266.519us	50	50	100.00
		lc_ctrl_sec_cm	39.970s	2.616ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	36.920s	266.519us	50	50	100.00
		lc_ctrl_sec_cm	39.970s	2.616ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	36.920s	266.519us	50	50	100.00
		lc_ctrl_sec_cm	39.970s	2.616ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	36.920s	266.519us	50	50	100.00
		lc_ctrl_sec_cm	39.970s	2.616ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	36.920s	266.519us	50	50	100.00
		lc_ctrl_sec_cm	39.970s	2.616ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	36.920s	266.519us	50	50	100.00
		lc_ctrl_sec_cm	39.970s	2.616ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	36.920s	266.519us	50	50	100.00
		lc_ctrl_sec_cm	39.970s	2.616ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	15.450s	1.707ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	13.350s	458.641us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	27.530s	6.217ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	21.140s	1.973ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	21.140s	1.973ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	24.150s	3.977ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	18.310s	3.272ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	18.310s	3.272ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	35.081m	141.958ms	17	50	34.00
V3		TOTAL			17	50	34.00
		TOTAL			995	1030	96.60

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.87	97.99	95.68	93.38	97.67	98.55	98.51	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 27 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 27 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.74359695462561760286401037492336115859803395543693155899028175960888620334868
      Line 10356, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5910744856 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 5910744856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.lc_ctrl_stress_all_with_rand_reset.90294046442457523219439167858821795793149103970943953960337039840796173887993
      Line 2781, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 14271477836 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 14271477836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 25 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 5 failures:

  • Test lc_ctrl_stress_all has 2 failures.

    • 4.lc_ctrl_stress_all.64261143584203303842219286246367197810943810855807897246430866545735388099805
      Line 8071, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 37363646304 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 37363646304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 5.lc_ctrl_stress_all.93701345037594779232948176821038736888743745527830366458461188874691065194395
      Line 14413, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 11422687761 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 11422687761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 14.lc_ctrl_stress_all_with_rand_reset.115231380086484476325206568181941209881192218987462124086701629627190151286684
      Line 18806, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 46623517774 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 46623517774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 37.lc_ctrl_stress_all_with_rand_reset.70098542894384324764138467453207421509844257508491057056516220361015279095878
      Line 11265, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 23933716264 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 23933716264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• Error-[CNST-STOF] Constraint solver timeout failure has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 44.lc_ctrl_stress_all_with_rand_reset.71648701292764423789382613262141382012485906788663259475365877410438481989932
      Line 34718, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • 46.lc_ctrl_stress_all_with_rand_reset.90906209936911000457312639345150208121380751571256790640537466311631186261137
      Line 37771, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 23.lc_ctrl_stress_all_with_rand_reset.32979629765170013002112238850117678950196679402394131010764031903081363609303
      Line 24395, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 17195451731 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 17195451731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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