LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Thursday June 13 2024 19:02:12 UTC

GitHub Revision: 548a3880d8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 95435389850697596633112362018639443702533575559488568730544091582583938649085

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	8.210s	490.019us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.400s	22.805us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.090s	30.359us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.890s	449.793us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.780s	165.039us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.250s	30.593us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.090s	30.359us	20	20	100.00
		lc_ctrl_csr_aliasing	1.780s	165.039us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.720s	155.016us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	18.310s	1.253ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.960s	13.646us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.460s	483.849us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	38.450s	2.085ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	24.550s	3.789ms	49	50	98.00
V2	security_escalation	lc_ctrl_state_failure	38.450s	2.085ms	50	50	100.00
		lc_ctrl_prog_failure	5.460s	483.849us	50	50	100.00
		lc_ctrl_errors	24.550s	3.789ms	49	50	98.00
		lc_ctrl_security_escalation	18.510s	2.459ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.541m	12.670ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	20.660s	1.457ms	20	20	100.00
		lc_ctrl_jtag_errors	1.115m	2.290ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	15.230s	2.889ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	25.780s	1.574ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	20.660s	1.457ms	20	20	100.00
		lc_ctrl_jtag_errors	1.115m	2.290ms	20	20	100.00
		lc_ctrl_jtag_access	23.390s	1.759ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	38.330s	4.981ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	5.230s	190.405us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.430s	75.734us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	29.660s	5.519ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	20.580s	946.251us	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.780s	37.760us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	5.750s	279.433us	10	10	100.00
		lc_ctrl_jtag_alert_test	1.670s	353.707us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	45.820s	6.663ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.460s	20.222us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	13.943m	50.108ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.400s	74.986us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.680s	555.541us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.680s	555.541us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.400s	22.805us	5	5	100.00
		lc_ctrl_csr_rw	1.090s	30.359us	20	20	100.00
		lc_ctrl_csr_aliasing	1.780s	165.039us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.890s	38.358us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.400s	22.805us	5	5	100.00
		lc_ctrl_csr_rw	1.090s	30.359us	20	20	100.00
		lc_ctrl_csr_aliasing	1.780s	165.039us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.890s	38.358us	20	20	100.00
V2		TOTAL			698	700	99.71
V2S	tl_intg_err	lc_ctrl_sec_cm	38.770s	3.677ms	5	5	100.00
		lc_ctrl_tl_intg_err	4.230s	227.356us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.230s	227.356us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	18.310s	1.253ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	38.450s	2.085ms	50	50	100.00
		lc_ctrl_sec_cm	38.770s	3.677ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	38.450s	2.085ms	50	50	100.00
		lc_ctrl_sec_cm	38.770s	3.677ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	38.450s	2.085ms	50	50	100.00
		lc_ctrl_sec_cm	38.770s	3.677ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	38.450s	2.085ms	50	50	100.00
		lc_ctrl_sec_cm	38.770s	3.677ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	38.450s	2.085ms	50	50	100.00
		lc_ctrl_sec_cm	38.770s	3.677ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	38.450s	2.085ms	50	50	100.00
		lc_ctrl_sec_cm	38.770s	3.677ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	38.450s	2.085ms	50	50	100.00
		lc_ctrl_sec_cm	38.770s	3.677ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	38.450s	2.085ms	50	50	100.00
		lc_ctrl_sec_cm	38.770s	3.677ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	18.510s	2.459ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.720s	155.016us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	25.780s	1.574ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	26.810s	1.303ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	26.810s	1.303ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	22.980s	565.087us	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	16.230s	2.327ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	16.230s	2.327ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	35.451m	27.113ms	17	50	34.00
V3		TOTAL			17	50	34.00
		TOTAL			995	1030	96.60

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	25	92.59
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.24	97.99	95.95	93.38	100.00	98.55	98.51	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 30 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 30 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.18509510843817106188638058903839366570998152028995133417510633471770854971986
      Line 15383, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 46962280910 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 46962280910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.lc_ctrl_stress_all_with_rand_reset.95926573853670904787176138839175692663090967305311277361386402885220507007640
      Line 36966, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 58466034614 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 58466034614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 28 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 42.lc_ctrl_stress_all_with_rand_reset.31707880849453030278601670984064366853869748041819665767452994220676373190518
      Line 20598, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 24109397838 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 24109397838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_stress_all has 1 failures.

    • 43.lc_ctrl_stress_all.74746780711255106502299246956538522801030553620098162065369986673857097336371
      Line 6730, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 23099404387 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 23099404387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_errors has 1 failures.

    • 1.lc_ctrl_errors.53738827371330703302639227024762794292516916487959520253652287241334026991692
      Line 1730, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_errors/latest/run.log

        UVM_ERROR @ 159403916 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 159403916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 14.lc_ctrl_stress_all_with_rand_reset.4100971534893211575718537905587719527162482627014223847625991748253884941112
      Line 28338, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 26.lc_ctrl_stress_all_with_rand_reset.30519613599902100678872926326527545497079671767992568256429993422831167616859
      Line 20423, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 66418787053 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 66418787053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.06.12_04.50.28
• 2024.06.11_11.53.03
• 2024.06.10_06.40.18
• 2024.06.08_13.05.52
• 2024.06.07_04.49.25
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• 2024.06.05_03.52.14