LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Friday June 21 2024 23:02:45 UTC

GitHub Revision: de38ce313c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 40294666978553523170681160506532247841705182588034413483474981853853670477454

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	4.550s	412.605us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	0.960s	14.985us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.120s	16.969us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	3.080s	150.352us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.350s	23.954us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.610s	79.801us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.120s	16.969us	20	20	100.00
		lc_ctrl_csr_aliasing	1.350s	23.954us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.440s	46.613us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	17.970s	322.150us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.990s	12.763us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.120s	525.706us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	37.940s	448.955us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	28.040s	641.796us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	37.940s	448.955us	50	50	100.00
		lc_ctrl_prog_failure	5.120s	525.706us	50	50	100.00
		lc_ctrl_errors	28.040s	641.796us	50	50	100.00
		lc_ctrl_security_escalation	20.880s	610.357us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.637m	4.245ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	23.330s	1.678ms	20	20	100.00
		lc_ctrl_jtag_errors	1.578m	39.988ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	13.350s	2.046ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	27.830s	3.398ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	23.330s	1.678ms	20	20	100.00
		lc_ctrl_jtag_errors	1.578m	39.988ms	20	20	100.00
		lc_ctrl_jtag_access	32.990s	5.694ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	35.380s	5.018ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	2.540s	398.058us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.570s	89.179us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	55.430s	10.396ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	9.070s	2.497ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.030s	91.069us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	6.280s	988.797us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.280s	222.081us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	25.240s	6.478ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.350s	20.036us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	8.556m	16.334ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.310s	118.538us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.110s	280.482us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.110s	280.482us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	0.960s	14.985us	5	5	100.00
		lc_ctrl_csr_rw	1.120s	16.969us	20	20	100.00
		lc_ctrl_csr_aliasing	1.350s	23.954us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.980s	47.970us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	0.960s	14.985us	5	5	100.00
		lc_ctrl_csr_rw	1.120s	16.969us	20	20	100.00
		lc_ctrl_csr_aliasing	1.350s	23.954us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.980s	47.970us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	41.950s	841.392us	5	5	100.00
		lc_ctrl_tl_intg_err	4.210s	725.824us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.210s	725.824us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	17.970s	322.150us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	37.940s	448.955us	50	50	100.00
		lc_ctrl_sec_cm	41.950s	841.392us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	37.940s	448.955us	50	50	100.00
		lc_ctrl_sec_cm	41.950s	841.392us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	37.940s	448.955us	50	50	100.00
		lc_ctrl_sec_cm	41.950s	841.392us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	37.940s	448.955us	50	50	100.00
		lc_ctrl_sec_cm	41.950s	841.392us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	37.940s	448.955us	50	50	100.00
		lc_ctrl_sec_cm	41.950s	841.392us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	37.940s	448.955us	50	50	100.00
		lc_ctrl_sec_cm	41.950s	841.392us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	37.940s	448.955us	50	50	100.00
		lc_ctrl_sec_cm	41.950s	841.392us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	37.940s	448.955us	50	50	100.00
		lc_ctrl_sec_cm	41.950s	841.392us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	20.880s	610.357us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.440s	46.613us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	27.830s	3.398ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	30.360s	1.547ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	30.360s	1.547ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	26.440s	2.712ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	21.120s	4.106ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	21.120s	4.106ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	53.325m	159.164ms	21	50	42.00
V3		TOTAL			21	50	42.00
		TOTAL			1001	1030	97.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.22	97.99	95.77	93.38	100.00	98.55	98.76	96.11

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 26 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 26 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.36420387211585717549141984245323820897153632269813956523167528183231748678528
      Line 25177, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 392911832958 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 392911832958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.lc_ctrl_stress_all_with_rand_reset.76422728962288384848978003067823793625151671612736303941195514525270762698367
      Line 8305, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 14444581015 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 14444581015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 24 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 3 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 23.lc_ctrl_stress_all_with_rand_reset.46852099498909685617597171485489818831338265534356620046103988133341948992767
      Line 21977, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 39210805266 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 39210805266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 41.lc_ctrl_stress_all_with_rand_reset.41573262203389270702033381349058507420794522537334417162829053703007287459395
      Line 4492, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 32967194327 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 32967194327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

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