LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Saturday June 22 2024 23:02:20 UTC

GitHub Revision: 8fdb25c8d9

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 116774179587740886356693500529232784059703555433764635649168222249757162669

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	5.810s	197.286us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.200s	20.137us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.160s	18.732us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	3.050s	387.295us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.310s	40.036us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.670s	32.164us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.160s	18.732us	20	20	100.00
		lc_ctrl_csr_aliasing	1.310s	40.036us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.730s	127.379us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	23.190s	712.697us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.960s	11.601us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	6.430s	150.358us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	36.090s	542.685us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	20.370s	970.340us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	36.090s	542.685us	50	50	100.00
		lc_ctrl_prog_failure	6.430s	150.358us	50	50	100.00
		lc_ctrl_errors	20.370s	970.340us	50	50	100.00
		lc_ctrl_security_escalation	16.890s	859.375us	50	50	100.00
		lc_ctrl_jtag_state_failure	2.280m	8.153ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	22.810s	7.478ms	20	20	100.00
		lc_ctrl_jtag_errors	1.103m	6.264ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	16.000s	629.491us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	28.950s	1.985ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	22.810s	7.478ms	20	20	100.00
		lc_ctrl_jtag_errors	1.103m	6.264ms	20	20	100.00
		lc_ctrl_jtag_access	28.910s	12.837ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	26.650s	2.306ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.230s	107.817us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.250s	65.287us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	17.460s	1.394ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	13.600s	2.268ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.010s	49.132us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	7.190s	293.796us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.200s	172.625us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	23.340s	3.733ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.220s	32.557us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	9.127m	18.358ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.350s	23.943us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.860s	125.286us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.860s	125.286us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.200s	20.137us	5	5	100.00
		lc_ctrl_csr_rw	1.160s	18.732us	20	20	100.00
		lc_ctrl_csr_aliasing	1.310s	40.036us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.890s	40.862us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.200s	20.137us	5	5	100.00
		lc_ctrl_csr_rw	1.160s	18.732us	20	20	100.00
		lc_ctrl_csr_aliasing	1.310s	40.036us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.890s	40.862us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	38.100s	215.519us	5	5	100.00
		lc_ctrl_tl_intg_err	4.180s	664.347us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.180s	664.347us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	23.190s	712.697us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	36.090s	542.685us	50	50	100.00
		lc_ctrl_sec_cm	38.100s	215.519us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	36.090s	542.685us	50	50	100.00
		lc_ctrl_sec_cm	38.100s	215.519us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	36.090s	542.685us	50	50	100.00
		lc_ctrl_sec_cm	38.100s	215.519us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	36.090s	542.685us	50	50	100.00
		lc_ctrl_sec_cm	38.100s	215.519us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	36.090s	542.685us	50	50	100.00
		lc_ctrl_sec_cm	38.100s	215.519us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	36.090s	542.685us	50	50	100.00
		lc_ctrl_sec_cm	38.100s	215.519us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	36.090s	542.685us	50	50	100.00
		lc_ctrl_sec_cm	38.100s	215.519us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	36.090s	542.685us	50	50	100.00
		lc_ctrl_sec_cm	38.100s	215.519us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	16.890s	859.375us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.730s	127.379us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	28.950s	1.985ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	22.400s	1.487ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	22.400s	1.487ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	22.350s	3.743ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	18.590s	598.439us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	18.590s	598.439us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	57.913m	37.786ms	27	50	54.00
V3		TOTAL			27	50	54.00
		TOTAL			1006	1030	97.67

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.33	97.99	95.95	93.38	100.00	98.55	99.00	96.47

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 18 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 18 failures.

    • 3.lc_ctrl_stress_all_with_rand_reset.34880410393183831672793433861173294237459183568768197642296402102720062176896
      Line 13312, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 26541144015 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 26541144015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 8.lc_ctrl_stress_all_with_rand_reset.26170478460410893106947765759454209241873177777445942209714596260328769889195
      Line 1080, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4337590074 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 4337590074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 16 more failures.

• Error-[CNST-STOF] Constraint solver timeout failure has 3 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.106259161828495992176080816670581107229834209457706771303729201001664431684883
      Line 38000, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • 40.lc_ctrl_stress_all_with_rand_reset.18348381392777169740482443370307416179066910179217185420272465021924934154042
      Line 49650, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • ... and 1 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 45.lc_ctrl_stress_all_with_rand_reset.67957159007627239779856253002962667909873554522451456541943823768386138556637
      Line 12348, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 25769054936 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 25769054936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_stress_all has 1 failures.

    • 46.lc_ctrl_stress_all.41106986773968241678466155493684619976998230594990883110981641341799873300777
      Line 2474, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 14626588595 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 14626588595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.106237650008405583575371646619323804868873474705149810093721548714768829525054
      Line 25447, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 16339553564 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 16339553564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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