LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Sunday June 23 2024 23:02:35 UTC

GitHub Revision: 25e609d6bb

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 43520053114197278442322840927374150239284669988213580416404649115121474470865

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	7.740s	109.471us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.020s	76.880us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.210s	19.183us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.650s	66.607us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.340s	58.828us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.930s	85.379us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.210s	19.183us	20	20	100.00
		lc_ctrl_csr_aliasing	1.340s	58.828us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	11.180s	321.308us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	25.140s	361.323us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.950s	27.287us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.770s	124.977us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	36.880s	517.967us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	26.610s	1.493ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	36.880s	517.967us	50	50	100.00
		lc_ctrl_prog_failure	4.770s	124.977us	50	50	100.00
		lc_ctrl_errors	26.610s	1.493ms	50	50	100.00
		lc_ctrl_security_escalation	17.070s	496.958us	50	50	100.00
		lc_ctrl_jtag_state_failure	2.192m	41.644ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	18.280s	672.847us	20	20	100.00
		lc_ctrl_jtag_errors	2.065m	5.014ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	13.090s	3.535ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	26.040s	814.235us	20	20	100.00
		lc_ctrl_jtag_prog_failure	18.280s	672.847us	20	20	100.00
		lc_ctrl_jtag_errors	2.065m	5.014ms	20	20	100.00
		lc_ctrl_jtag_access	19.020s	3.261ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	35.790s	1.215ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	2.880s	363.797us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.440s	296.583us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	43.680s	15.604ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	14.710s	2.028ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.950s	45.980us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	6.180s	436.432us	10	10	100.00
		lc_ctrl_jtag_alert_test	1.900s	50.357us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	11.640s	4.911ms	9	10	90.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.350s	71.779us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	12.948m	23.575ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.260s	18.338us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.630s	129.806us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.630s	129.806us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.020s	76.880us	5	5	100.00
		lc_ctrl_csr_rw	1.210s	19.183us	20	20	100.00
		lc_ctrl_csr_aliasing	1.340s	58.828us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.030s	96.591us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.020s	76.880us	5	5	100.00
		lc_ctrl_csr_rw	1.210s	19.183us	20	20	100.00
		lc_ctrl_csr_aliasing	1.340s	58.828us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.030s	96.591us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	50.050s	229.864us	5	5	100.00
		lc_ctrl_tl_intg_err	3.120s	2.076ms	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	3.120s	2.076ms	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	25.140s	361.323us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	36.880s	517.967us	50	50	100.00
		lc_ctrl_sec_cm	50.050s	229.864us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	36.880s	517.967us	50	50	100.00
		lc_ctrl_sec_cm	50.050s	229.864us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	36.880s	517.967us	50	50	100.00
		lc_ctrl_sec_cm	50.050s	229.864us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	36.880s	517.967us	50	50	100.00
		lc_ctrl_sec_cm	50.050s	229.864us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	36.880s	517.967us	50	50	100.00
		lc_ctrl_sec_cm	50.050s	229.864us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	36.880s	517.967us	50	50	100.00
		lc_ctrl_sec_cm	50.050s	229.864us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	36.880s	517.967us	50	50	100.00
		lc_ctrl_sec_cm	50.050s	229.864us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	36.880s	517.967us	50	50	100.00
		lc_ctrl_sec_cm	50.050s	229.864us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	17.070s	496.958us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.180s	321.308us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	26.040s	814.235us	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	21.720s	1.087ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	21.720s	1.087ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	22.380s	1.270ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	19.980s	1.288ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	19.980s	1.288ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	26.714m	66.478ms	22	50	44.00
V3		TOTAL			22	50	44.00
		TOTAL			1001	1030	97.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.84	97.99	95.59	93.38	97.67	98.55	98.76	95.94

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 24 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.53973296754057865726002728562882204925992542253918929827344474359651011620543
      Line 6120, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 16157346027 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 16157346027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.lc_ctrl_stress_all_with_rand_reset.68451807029596916378884934974693919338000425861755042704199704269854340761376
      Line 23076, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 14469579857 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 14469579857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 22 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 4.lc_ctrl_stress_all_with_rand_reset.84536451354701499182356389707147117291171507425914540548686906313211937420742
      Line 1655, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5515688928 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 5515688928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 7.lc_ctrl_stress_all_with_rand_reset.109944032061038155005271263607535229847196917779768239725224429650571882948952
      Line 39381, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 43767265475 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 43767265475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (lc_ctrl_jtag_priority_vseq.sv:113) [lc_ctrl_jtag_priority_vseq] timeout occurred! has 1 failures:

  • Test lc_ctrl_jtag_priority has 1 failures.

    • 7.lc_ctrl_jtag_priority.40596099809118394378685726286341967234583000144251874184077128223087998758149
      Line 509, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_priority/latest/run.log

        UVM_FATAL @ 10008160553 ps: (lc_ctrl_jtag_priority_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.lc_ctrl_jtag_priority_vseq] timeout occurred!
        UVM_INFO @ 10008160553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 19.lc_ctrl_stress_all_with_rand_reset.68138230205098605257851169756924378679104878619537117790416317100747213643068
      Line 14287, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 22591363509 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 22591363509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 32.lc_ctrl_stress_all_with_rand_reset.15046938657888769906795467462620812044575924419959084023602674549877770887711
      Line 22983, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

Past Results

• Latest
• 2024.06.23_07.50.28
• 2024.06.22_11.35.08
• 2024.06.14_07.14.50
• 2024.06.12_04.50.28
• 2024.06.11_11.53.03
• 2024.06.10_06.40.18
• 2024.06.08_13.05.52