LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Monday June 24 2024 23:02:35 UTC

GitHub Revision: 6e698b4dfe

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 102849012855470111388983783327793201144267754054590670930996118558901483180117

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	9.590s	331.488us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.250s	74.052us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.120s	48.382us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.770s	247.113us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.690s	55.386us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.410s	32.129us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.120s	48.382us	20	20	100.00
		lc_ctrl_csr_aliasing	1.690s	55.386us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.870s	103.235us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	25.470s	916.346us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.020s	12.010us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.310s	298.229us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	42.070s	370.567us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	26.610s	2.640ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	42.070s	370.567us	50	50	100.00
		lc_ctrl_prog_failure	4.310s	298.229us	50	50	100.00
		lc_ctrl_errors	26.610s	2.640ms	50	50	100.00
		lc_ctrl_security_escalation	17.950s	502.483us	50	50	100.00
		lc_ctrl_jtag_state_failure	2.506m	19.269ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	18.660s	678.413us	20	20	100.00
		lc_ctrl_jtag_errors	1.574m	4.896ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	14.740s	673.445us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	38.890s	2.370ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	18.660s	678.413us	20	20	100.00
		lc_ctrl_jtag_errors	1.574m	4.896ms	20	20	100.00
		lc_ctrl_jtag_access	26.600s	4.796ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	31.590s	14.928ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	6.820s	3.185ms	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.530s	81.812us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	30.080s	1.381ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	19.980s	1.796ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.690s	150.942us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	7.250s	1.134ms	10	10	100.00
		lc_ctrl_jtag_alert_test	2.510s	76.820us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	46.240s	5.695ms	9	10	90.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.380s	43.282us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	9.278m	82.615ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.350s	82.926us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.200s	142.229us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.200s	142.229us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.250s	74.052us	5	5	100.00
		lc_ctrl_csr_rw	1.120s	48.382us	20	20	100.00
		lc_ctrl_csr_aliasing	1.690s	55.386us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.890s	39.904us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.250s	74.052us	5	5	100.00
		lc_ctrl_csr_rw	1.120s	48.382us	20	20	100.00
		lc_ctrl_csr_aliasing	1.690s	55.386us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.890s	39.904us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	41.360s	209.940us	5	5	100.00
		lc_ctrl_tl_intg_err	4.240s	103.342us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.240s	103.342us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	25.470s	916.346us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	42.070s	370.567us	50	50	100.00
		lc_ctrl_sec_cm	41.360s	209.940us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	42.070s	370.567us	50	50	100.00
		lc_ctrl_sec_cm	41.360s	209.940us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	42.070s	370.567us	50	50	100.00
		lc_ctrl_sec_cm	41.360s	209.940us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	42.070s	370.567us	50	50	100.00
		lc_ctrl_sec_cm	41.360s	209.940us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	42.070s	370.567us	50	50	100.00
		lc_ctrl_sec_cm	41.360s	209.940us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	42.070s	370.567us	50	50	100.00
		lc_ctrl_sec_cm	41.360s	209.940us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	42.070s	370.567us	50	50	100.00
		lc_ctrl_sec_cm	41.360s	209.940us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	42.070s	370.567us	50	50	100.00
		lc_ctrl_sec_cm	41.360s	209.940us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	17.950s	502.483us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.870s	103.235us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	38.890s	2.370ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	28.710s	2.716ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	28.710s	2.716ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	29.620s	3.736ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	17.160s	501.414us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	17.160s	501.414us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.792h	56.772ms	26	50	52.00
V3		TOTAL			26	50	52.00
		TOTAL			1005	1030	97.57

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.83	97.99	95.14	93.38	97.67	98.55	98.76	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 19 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 19 failures.

    • 2.lc_ctrl_stress_all_with_rand_reset.91156194239209090735584120135782940121602868937580125714525461831738538509054
      Line 44054, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 85697318090 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 85697318090 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.lc_ctrl_stress_all_with_rand_reset.86021798089346384167415824817585639856218299524596239037481413626698480295335
      Line 21655, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 73979857855 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 73979857855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 17 more failures.

• Error-[CNST-STOF] Constraint solver timeout failure has 3 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 15.lc_ctrl_stress_all_with_rand_reset.86862431037371678496487169431844353588141201579158043781343477778564337350476
      Line 82961, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • 21.lc_ctrl_stress_all_with_rand_reset.47410939738546454198628742816543523118956066092807330158658071842267421767776
      Line 58128, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • ... and 1 more failures.

• UVM_FATAL (lc_ctrl_jtag_priority_vseq.sv:135) [lc_ctrl_jtag_priority_vseq] wait for simultaneous mutex claim has 1 failures:

  • Test lc_ctrl_jtag_priority has 1 failures.

    • 0.lc_ctrl_jtag_priority.75437703835898387418676484063307176755130564088898756138067491008358061049952
      Line 691, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_priority/latest/run.log

        UVM_FATAL @ 22015728501 ps: (lc_ctrl_jtag_priority_vseq.sv:135) [uvm_test_top.env.virtual_sequencer.lc_ctrl_jtag_priority_vseq] wait for simultaneous mutex claim
        UVM_INFO @ 22015728501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 9.lc_ctrl_stress_all_with_rand_reset.100468391137639505627006821448884142645005946270258674802860784649245869943689
      Line 42588, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 199596636343 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 199596636343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 38.lc_ctrl_stress_all_with_rand_reset.34370632298385307753394814623727147084777364062250000256216029019531183042563
      Line 24563, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 58185813098 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 58185813098 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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